PTAB

IPR2018-00855

Intel Corp v. Godo Kaisha IP Bridge 1

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’289 patent discloses a semiconductor device, such as a metal-insulator-semiconductor field effect transistor (MISFET), that incorporates an internal stress film. This film is designed to generate stress in the transistor's channel region to increase the mobility of charge carriers, thereby improving device performance.

3. Grounds for Unpatentability

Ground 1: Claims 1-4, 6-27, and 29 are obvious over Xiang in view of Shimizu and Kumagai.

  • Prior Art Relied Upon: Xiang (Patent 6,437,404), Shimizu (WO 02/43151), and Kumagai (WO 02/47167).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Xiang disclosed a MOSFET transistor with the fundamental structure required by independent claim 1. Specifically, Xiang taught a silicon nitride etch stop layer formed over the source/drain regions but not on the upper surface of the gate electrode. While Xiang’s primary purpose for this layer was as an etch stop, its structure and placement met the core limitations of the claim.
    • Motivation to Combine: A person of ordinary skill in the art (POSA) would combine the teachings of Shimizu and Kumagai with Xiang to improve device performance, a central goal in semiconductor design. Both Shimizu and Kumagai explicitly taught using silicon nitride films to impart stress (tensile for n-channel, compressive for p-channel) in the gate length direction to increase carrier mobility. A POSA would have been motivated to modify the deposition process of Xiang's silicon nitride etch stop layer to make it stress-inducing, as taught by Shimizu and Kumagai. Kumagai provided a further, compelling motivation by teaching that stressed silicon nitride films also function as superior etch stoppers, thus enhancing Xiang's originally disclosed purpose while simultaneously improving performance.
    • Expectation of Success: The combination was asserted to be predictable. Shimizu disclosed specific, exemplary process parameters (e.g., plasma CVD wattage) for depositing silicon nitride films to achieve desired tensile or compressive stresses. This demonstrated that creating such stressed films was a well-understood technique with predictable outcomes, giving a POSA a reasonable expectation of success.

Ground 2: Claim 5 is obvious over Xiang, Shimizu, and Kumagai in view of En.

  • Prior Art Relied Upon: Xiang (Patent 6,437,404), Shimizu (WO 02/43151), Kumagai (WO 02/47167), and En (Patent 6,573,172).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claim 5, which adds the limitation of an internal stress film formed above the source/drain regions with a "thin film interposed therebetween." Petitioner established the base combination of Xiang, Shimizu, and Kumagai as in Ground 1. En was introduced to teach the interposed thin film.
    • Motivation to Combine: En taught using a thin oxide layer interposed between the source/drain regions and an overlying stress film. The purpose of En’s interposed layer was to aid in selectively applying differently stressed films over different transistor types (nMOS vs. pMOS) on the same wafer. A POSA would combine En's teaching with the base combination to solve a known problem discussed in Kumagai: the need to apply different types of stress (tensile vs. compressive) to achieve performance gains in both n-type and p-type transistors. En’s technique provided a practical method for achieving the differentiated stress profiles taught by Kumagai.
    • Expectation of Success: En demonstrated that a stress film could still effectively impart stress to the channel region even with its thin oxide layer interposed, providing a POSA a clear basis to expect the combination would work as intended.

Ground 3: Claim 10 is obvious over Xiang, Shimizu, Kumagai, and Buynoski.

  • Prior Art Relied Upon: Xiang (Patent 6,437,404), Shimizu (WO 02/43151), Kumagai (WO 02/47167), and Buynoski (Patent 5,729,045).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claim 10, which requires the semiconductor substrate to have a principal surface on a {100} plane and the gate length direction to be substantially in a <011> direction.
    • Motivation to Combine: A POSA seeking to optimize the performance of the transistor from the primary combination would have been motivated to use the specific crystallographic orientation of claim 10. Kumagai explicitly disclosed performance data for its stress films on a transistor fabricated on a Si (001) surface (equivalent to the claimed {100} plane) with a drain current parallel to the <110> axis (equivalent to the claimed <011> direction). Furthermore, Buynoski taught that this specific orientation was well-known and optimal for fabricating FETs because it inherently provides higher carrier mobility. This provided a strong, independent motivation to configure the base transistor of Xiang with this known, preferred orientation to maximize performance.
    • Expectation of Success: The teachings of both Kumagai and Buynoski confirmed that using this orientation was a predictable, conventional design choice for improving device speed, not an inventive step.

4. Key Claim Construction Positions

  • "gate length direction": Petitioner argued this term should be construed as "the direction in which charge carriers move." This construction was based on explicit definitions within the ’289 patent’s specification, which stated that tensile stress is generated parallel to "the direction in which carriers move (i.e., the gate length direction)." This construction was central to the obviousness arguments, as the prior art taught applying stress along the direction of current flow to enhance carrier mobility.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-27 and 29 of the ’289 patent as unpatentable.