PTAB

IPR2018-00989

Micron Technology Inc v. North Star Innovations Inc

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1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Amplifying a Signal to Produce a Latched Digital Signal
  • Brief Description: The ’274 patent relates to output stages for memory integrated circuits. The disclosed invention is directed at providing a "clock-free" latch within the output stage, which purportedly solves timing problems associated with prior art systems that allegedly required multiple, difficult-to-synchronize clock signals.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 8-12, 14-16, 20, and 21 are anticipated by Tachibana under 35 U.S.C. §102.

  • Prior Art Relied Upon: Tachibana (Japanese Patent Pub. H4-170816).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tachibana, particularly the embodiments in its Figures 15 and 17, discloses every element of the challenged claims. For independent claim 1, Petitioner asserted that Tachibana teaches an apparatus for use as an output stage of a memory device that includes all recited components. Petitioner identified Tachibana’s circuits in Figures 8 and 9 as the claimed "timing circuit," the single-stage amplifier in Figures 15 and 17 as the "differential amplifier," and PMOS transistor 412 as the "impedance control circuit." Further, Petitioner mapped Tachibana’s ECL-MOS conversion circuit to the claimed "level converter" and argued that the cross-coupled inverters 604 and 629 constitute the claimed "clock-free latch" because they respond only to the level converter's output and not to a separate clock signal. Petitioner applied similar element-by-element mapping for the dependent claims.

Ground 2: Claims 4-7 are obvious over Tachibana in view of a POSA's knowledge under 35 U.S.C. §103.

  • Prior Art Relied Upon: Tachibana (Japanese Patent Pub. H4-170816) and the general knowledge of a Person of Ordinary Skill in the Art (POSA).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that dependent claims 4-7, which add limitations related to the timing circuit receiving a clock signal, would have been obvious modifications to the circuit disclosed in Tachibana. Petitioner argued that while Tachibana primarily discloses an asynchronous memory device, it expressly states that control signals "can easily be generated from the standard clock" where one is available, such as in a synchronous RAM (STRAM). This modification would satisfy the limitation of claim 4 requiring the timing circuit to receive a clock signal. The remaining dependent claims 5-7, which rely on this modification, would be obvious for the same reasons.
    • Motivation to Combine: A POSITA would combine Tachibana's circuit with the common knowledge of using a standard clock input to gain the well-known speed and timing advantages of synchronous memory devices, which were faster and more predictable than asynchronous devices. Tachibana itself provided the motivation by explicitly suggesting this adaptation.
    • Expectation of Success: A POSITA would have had a high expectation of success in making this modification. The use of an external clock to generate internal timing signals was a fundamental, routine, and well-understood practice in memory circuit design, and Tachibana's express teaching confirmed the feasibility of the approach.

Ground 3: Claims 22 and 23 are obvious over Tachibana in view of Hanamura under 35 U.S.C. §103.

  • Prior Art Relied Upon: Tachibana (Japanese Patent Pub. H4-170816) and Hanamura (Patent 4,891,792).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Tachibana’s BiCMOS memory discloses the base memory device of claim 21, upon which claims 22 and 23 depend. To render claim 22 obvious, Petitioner cited Hanamura for its disclosure of a memory device featuring a plurality of output stages and data outputs, enabling parallel data output. To render claim 23 obvious, Petitioner relied on Hanamura's teaching of a "bit lines load" circuit that couples a memory array to sense amplifiers.
    • Motivation to Combine: A POSITA would combine Tachibana's output buffer with Hanamura's teaching of multiple output stages to achieve faster memory access and improved bandwidth, a widely recognized benefit in memory system design. Similarly, a POSITA would have been motivated to incorporate a bit line load array as taught by Hanamura into Tachibana’s design to enable precharging of the bit lines. Precharging was a ubiquitous and well-known technique used to improve data access speeds and overall performance.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in both combinations. The memory architectures in Tachibana and Hanamura were structurally similar, making integration straightforward. Implementing parallel output paths and bit-line precharging were common, routine design choices for improving memory performance, and Tachibana’s disclosure of a "data line load MOS" transistor suggested inherent compatibility with Hanamura's teachings.

4. Relief Requested

  • Petitioner requests that the Board institute an inter partes review and find claims 1-12, 14-16, and 20-23 of the ’274 patent unpatentable.