PTAB

IPR2018-01034

Intel Corp v. VLSI Technology LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory with Low Voltage Operation
  • Brief Description: The ’806 patent describes a device for reducing power consumption in an integrated circuit using two distinct memories. A "first memory" operates at a higher voltage, while a "second memory" with a different cell topology operates at a lower voltage and stores status data for the first memory, allowing the first memory to enter a low-power state.

3. Grounds for Unpatentability

Ground 1: Claims 11-13, 15, and 17 are obvious over Shuckle, Kojima, Chang, Flautner, and Keltcher.

  • Prior Art Relied Upon: Shuckle (Patent 7,017,054), Kojima (Patent 5,687,382), Chang (Patent 7,106,620), Flautner (a 2002 IEEE publication), and Keltcher (a 2003 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of references taught every limitation of the challenged claims. Shuckle was asserted to disclose the core architecture: a "first memory" (L2 cache) and a "second memory" (a "mirror tag" memory) that stores status information about the first. Shuckle also taught a "first mode" (high power state) where both memories are accessible and a "second mode" (low power state) where the first memory is inaccessible but the second remains active for snoop operations.
    • To meet the remaining limitations, Petitioner argued a POSITA would combine Shuckle with other references. Kojima taught using two memories with different minimum operating voltages (one high-voltage, one low-voltage) to reduce power, which would be applied to Shuckle’s L2 cache and mirror tag. Chang taught using different SRAM cell topologies (e.g., 6T vs. 8T SRAM) to achieve the different voltage and performance characteristics described by Kojima. Flautner taught putting a cache into a low-power "drowsy mode" by supplying a lower voltage, which would achieve the "second mode of operation" for Shuckle’s L2 cache. Finally, Keltcher taught integrating the memory controller and L2 cache on a single chip, making it obvious to locate Shuckle’s first and second memories on the same integrated circuit.
    • Motivation to Combine: Petitioner contended a POSITA would combine these references to achieve predictable benefits. The primary motivation was to reduce power consumption, a stated goal of both Shuckle and Kojima. A POSITA would combine Shuckle with Kojima and Chang to optimize the power usage of Shuckle’s two-memory system by implementing the more frequently accessed mirror tag with low-voltage, 8T SRAM cells and the larger L2 cache with higher-voltage, area-efficient 6T SRAM cells. Flautner would be incorporated to further reduce leakage power in the L2 cache, consistent with Shuckle’s overall objective. Keltcher would be used because Shuckle expressly suggests using AMD processors, and Keltcher describes an improved AMD processor with an on-chip memory controller that would be a natural choice for integration.
    • Expectation of Success: Petitioner argued that success was reasonably expected because the combination involved applying known techniques (e.g., using different memory cells, applying lower voltages for low-power modes) to a conventional cache architecture to achieve the predictable result of improved power efficiency.

Ground 2: Claims 11-13, 15, and 17 are obvious over Shuckle, Kojima, Chang, and Keltcher (contingent on claim construction).

  • Prior Art Relied Upon: Shuckle (Patent 7,017,054), Kojima (Patent 5,687,382), Chang (Patent 7,106,620), and Keltcher (a 2003 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground is asserted as an alternative if the Board does not adopt Petitioner's proposed construction of "second mode of operation." Petitioner argued that all claim limitations are met by this combination for the same reasons as in Ground 1, with the exception of limitation 11[j] ("to access the second memory but not the first memory when in a second mode of operation"). Under this contingent ground, Petitioner asserted that Shuckle alone discloses this limitation without needing Flautner. Shuckle explicitly teaches that in its low-power C2/C3 states, the processor’s caches are "unable to perform" snoops (i.e., are inaccessible), while the memory controller remains operable to access the mirror tag memory (the second memory) to perform those snoop operations.
    • Motivation to Combine (for §103 grounds): The motivations to combine Shuckle, Kojima, Chang, and Keltcher are identical to those asserted in Ground 1. The combination aimed to create a power-efficient, integrated cache system using known design choices for memory cell voltage and topology.
    • Expectation of Success (for §103 grounds): The expectation of success was based on the same rationale as Ground 1, as it involved the integration of well-understood technologies for predictable improvements.

4. Key Claim Construction Positions

  • Petitioner argued the term "second mode of operation" should be construed to mean "when a lower voltage is provided to the first and second memory."
    • This proposed construction was based on the patentee's own explicit definition provided during prosecution. Petitioner asserted that in a March 2009 amendment, the patentee added the term and clarified its meaning with an "i.e." (that is) statement, which constitutes a clear and unambiguous definition that limits the claim scope. This construction is critical for Ground 1, which relies on Flautner's teaching of applying a lower voltage to achieve a low-power state.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 11-13, 15, and 17 of the ’806 patent as unpatentable.