Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2018-01040
• Patent #: 7,706,207
• Filed: June 15, 2018
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-4, 9, 10, 12, and 13

2. Patent Overview

• Title: Memory Device with Combined Word Line Driver and Level Shifter
• Brief Description: The ’207 patent discloses computer memory circuitry that combines a word line driver and a voltage level shifter into a single circuit. The purported innovation is an arrangement of four transistors that performs both functions, intended to reduce circuit area and improve memory access speed in hierarchical memory structures.

3. Grounds for Unpatentability

Ground 1: Obviousness over Takahashi - Claims 1-4, 9, and 10 are obvious over Takahashi.

• Prior Art Relied Upon: Takahashi (Application # 2004/0041173).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Takahashi, which was not considered during prosecution, discloses the exact inventive concept of the ’207 patent. Specifically, Takahashi’s “third word decoder” is a combined local word line driver and voltage level shifter that uses the same four-transistor circuit topology recited in independent claim 1. Petitioner provided a detailed, transistor-by-transistor mapping of Takahashi’s circuit (transistors 221, 222, 223, and 224 in Fig. 15) to the circuit elements of claim 1. Takahashi also disclosed the hierarchical memory structure with global and local word lines that provides the context for claim 9.
  • Motivation to Combine (for §103 grounds): As a single-reference ground under 35 U.S.C. §103, the argument was that Takahashi itself renders the claims obvious because it discloses all claimed features in a single, integrated circuit design. No motivation to combine separate references was required for this ground.
  • Key Aspects: Petitioner contended that Takahashi disclosed the very combination purported to be the point of novelty in the ’207 patent, undermining the patent’s assertion of inventiveness over the prior art.

Ground 2: Obviousness over Takahashi and Jang - Claims 1-4 and 10 are obvious over Takahashi in view of Jang.

• Prior Art Relied Upon: Takahashi (Application # 2004/0041173) and Jang (K.R. Registered Patent No. 10-0557936).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative to Ground 1, addressing an embodiment shown in Figure 4 of the ’207 patent where separate voltage references are supplied to two of the transistors. While Takahashi disclosed the core four-transistor circuit, Jang explicitly taught an identical word line driver and level shifter circuit where the two pull-up transistors (P1 and P2) are connected to separate voltage sources. Petitioner argued that Jang’s circuit diagram corresponded exactly to the circuit of the ’207 patent’s Figure 4.
  • Motivation to Combine (for §103 grounds): A POSITA reviewing Takahashi’s circuit would combine its teachings with Jang because Jang demonstrated a known, alternative way to supply power to the exact same circuit topology. Modifying Takahashi’s single voltage line into separate lines as shown in Jang would have been an obvious design choice to explore different power management or performance characteristics.
  • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as the modification involved a routine and predictable change to the voltage supply scheme of an existing circuit, a common practice in circuit design.

Ground 3: Obviousness over Takahashi and Lu - Claim 12 is obvious over Takahashi in view of Lu.

• Prior Art Relied Upon: Takahashi (Application # 2004/0041173) and Lu (Patent 6,009,023).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground targeted dependent claim 12, which added limitations requiring transistors in different parts of the memory to have different gate oxide thicknesses. Petitioner established that Takahashi disclosed a dual-voltage memory system where some components (e.g., local word line drivers) operate in a higher, boosted voltage domain (Vbt), while others (e.g., global word line drivers) operate in a lower voltage domain (VDD). Lu taught the well-known principle of using thicker gate oxides for transistors in higher-voltage regions to ensure reliability and prevent breakdown, while using thinner gate oxides in lower-voltage regions to improve performance.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Lu’s teachings with Takahashi’s system to improve its overall reliability and performance. Applying Lu’s established design principles to Takahashi’s dual-voltage architecture was a straightforward engineering step to optimize the circuit.
  • Expectation of Success (for §103 grounds): The outcome was predictable, as using different gate oxide thicknesses based on operating voltage was a standard, well-understood technique in the art for improving memory device design.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Takahashi, Jang, and Lu for claim 12, and adding Krishnan (a 1999 IEEE article) to the combinations to teach the specific gate oxide thickness ranges recited in claim 13. These grounds relied on similar motivations to combine to further optimize the base circuit from Takahashi.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 9, 10, 12, and 13 of the ’207 patent as unpatentable.