Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2018-01107
• Patent #: 8,268,672
• Filed: June 13, 2018
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-5, 9, and 12

2. Patent Overview

• Title: Method of Assembling Two Chips, and Assembly of Two Chips
• Brief Description: The ’672 patent describes a method for assembling two semiconductor chips in a face-to-face, "chip-on-chip" configuration. The method involves using a fluid solder layer to create electrical interconnections and form an intermetallic compound between the bond pads of the two chips.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claim 9 under 35 U.S.C. §102

• Prior Art Relied Upon: Shibata (Application # 2002/0149117).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Shibata discloses every element of independent claim 9. Shibata teaches a chip-on-chip assembly comprising a first and second semiconductor chip with surfaces facing each other. Both chips have bond pads (termed "electrode terminals") exposed through openings in a passivation layer ("insulator film"). The chips are electrically connected via a solder interconnection (an Au-Sn alloy layer) sandwiched between a first underbump metallization and a second metallization. Shibata explicitly discloses that the solder layer (0.5-3.0 µm) is thinner than the underbump metallization layers (10-30 µm) and that heating causes the solder to diffuse into the metallization, forming an intermetallic compound at the interface.

Ground 2: Obviousness of Claims 1, 4, and 5 under 35 U.S.C. §103

• Prior Art Relied Upon: Pahl (A Thermode Bonding Process for Fine Pitch Flip Chip Applications Down to 40 Microns, 2001) in view of Shibata (Application # 2002/0149117).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Pahl teaches the core method of independent claim 1 but in the context of a chip-on-substrate assembly. Pahl describes applying solder caps onto an underbump metallization (UBM) using an immersion soldering process, where the solder is applied as a fluid layer and forms a contact angle of less than 90° for good wettability. During a thermode bonding process, the solder on the first component (a testchip) forms an intermetallic compound with the metallization on the second component (a silicon substrate). Shibata supplies the teaching of a true chip-on-chip assembly, disclosing a second active semiconductor chip to replace Pahl’s passive silicon substrate.
  • Motivation to Combine: A person of ordinary skill in the art (POSA) would combine these references to apply Pahl's advanced, fine-pitch immersion soldering technique to a more complex chip-on-chip device as taught by Shibata. Since Pahl demonstrated the success of its bonding process on silicon substrates, a POSA would be motivated to replace that substrate with an active silicon chip (like Shibata's second chip) to create a denser, more functional integrated package.
  • Expectation of Success: Both references describe flip-chip assembly using similar thermode bonding processes and material sets (e.g., Ni/Au metallizations). A POSA would have a reasonable expectation of success in combining the two, as it would amount to applying a known soldering technique to a known chip configuration, a predictable modification.

Ground 3: Obviousness of Claim 2 under 35 U.S.C. §103

• Prior Art Relied Upon: Pahl, Shibata, and Puttlitz (Area Array Interconnection Handbook, 2001).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination of Pahl and Shibata to further teach the limitation of dependent claim 2, which requires the metallization on the second chip to have a surface "flattened using electroplating." While Pahl and Shibata teach using electroless plating, Puttlitz explicitly teaches that electroless and electroplated nickel are common, interchangeable, and well-known alternatives for creating planar Ni/Au metallization layers.
  • Motivation to Combine: A POSA seeking to create a planarized metallization surface, as required by the claim, would have recognized from Puttlitz that electroplating was one of a finite number of well-understood, predictable methods to achieve this goal. The choice between electroless and electroplated deposition would have been a simple design choice based on available tools and desired surface properties.
  • Expectation of Success: As Puttlitz describes electroplating as a common substitute for electroless plating with predictable results (i.e., a planar Ni/Au layer), a POSA would have a high expectation of success in making this substitution in the Pahl/Shibata combination.

Ground 4: Obviousness of Claims 3 and 12 under 35 U.S.C. §103

• Prior Art Relied Upon: Shibata, Pahl, and Ference (Patent 6,225,699).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses the limitations of claims 3 and 12, which require the first chip to extend laterally beyond the second chip and to be provided with "further bumps of a larger height" for connecting to an external component. Shibata discloses a chip-on-chip assembly where the first chip extends beyond the second and has additional bond pads for external wire bonding. The combination with Pahl would apply a layer of solder to these external pads. Ference provides the final piece, teaching the use of larger solder balls/bumps to connect a similar stacked-chip assembly to a third component (e.g., a substrate or circuit board), with the larger bumps providing the necessary standoff height to clear the lower chip.
  • Motivation to Combine: A POSA would have been motivated to combine these teachings to solve the common and well-understood problem of connecting a chip-on-chip assembly to the rest of an electronic system. Ference provides a direct and explicit solution for this exact configuration by using solder bumps of different heights for inter-chip and chip-to-board connections.
  • Expectation of Success: Replacing Shibata's wire bonds with Ference's taller solder bumps is a simple application of a known packaging technique to a known structure. A POSA would have a high expectation that this method would successfully create a robust connection to an external board while providing the necessary physical clearance for the stacked-chip structure.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-5, 9, and 12 of the ’672 patent as unpatentable.