ARM Ltd. v. ATI Technologies ULC

1. Case Identification

• Case #: IPR2018-1149
• Patent #: 7,633,506
• Filed: May 25, 2018
• Petitioner(s): ARM Ltd. and ARM, Inc.
• Patent Owner(s): Advanced Micro Devices, Inc. and ATI Technologies ULC
• Challenged Claims: 1-9

2. Patent Overview

• Title: Parallel Pipeline Graphics System
• Brief Description: The ’506 patent discloses a graphics processing system featuring a front-end and a back-end with multiple parallel processing pipelines. Each pipeline processes a portion of a screen image and includes components like a scan converter, a z-buffer, a rasterizer, and a “unified shader” for performing both color and texture shading operations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Rubinstein and Collodi - Claims 1-9 are obvious over Rubinstein in view of Collodi.

• Prior Art Relied Upon: Rubinstein (Patent 7,102,646) and Collodi (Application # US 2003/0076320).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Rubinstein disclosed a graphics processor with a pipeline nearly identical to that claimed in the ’506 patent, including a front-end (geometry processor), a back-end (binning and rendering engines), screen space tiling, and a double-z scheme with hierarchical, early, and late z-buffering. The primary missing element in Rubinstein was the use of multiple parallel pipelines with a specific "unified shader." Petitioner argued that Collodi supplied these missing elements. Collodi disclosed a programmable per-pixel shader that performs both color and texture shading, meeting the "unified shader" limitation. Collodi also expressly taught that using multiple parallel processors for pixel throughput was desirable to increase rendering efficiency, thus disclosing the claimed parallel pipeline architecture. For dependent claims, Rubinstein was argued to teach a FIFO unit for load balancing (claim 2), a z-buffer logic unit (claim 3), and interfaces for hierarchical, early, and late z-buffering (claims 4-5).
  • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) would combine the references to achieve predictable benefits. Petitioner argued a POSITA implementing Rubinstein’s pipeline, which described a generic shading unit, would have looked to references like Collodi for an improved, programmable shader. The motivation was to improve performance and user customization, which were known benefits taught by Collodi. Implementing parallel pipelines was presented as a routine improvement and a simple duplication of the hardware disclosed in Rubinstein and Collodi, a technique expressly taught by Collodi to improve graphics efficiency.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because combining the references was a simple substitution of known elements. Both Rubinstein and Collodi described similar graphics pipelines, making the integration of Collodi’s programmable shader into Rubinstein’s system straightforward and the results predictable.

Ground 2: Obviousness over Rubinstein, Collodi, and Zatz - Claims 8-9 are obvious over Rubinstein in view of Collodi, in further view of Zatz.

• Prior Art Relied Upon: Rubinstein (Patent 7,102,646), Collodi (Application # US 2003/0076320), and Zatz (Patent 6,809,732).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative for claims 8 and 9, which required the unified shader to be operative to "loop back to process operations" for multipass shading. While Petitioner argued the primary combination of Rubinstein and Collodi taught this, Zatz was introduced to provide a more explicit teaching. Zatz disclosed a programmable shader with an explicit "Return Path" designed to allow the shader to process data in multiple passes. This directly taught the loopback functionality for multipass operations, as recited in claim 8. Zatz also taught that shader programs could contain separate sets of instructions for color and texture shading, addressing the limitations of claim 9.
  • Motivation to Combine (for §103 grounds): The motivation was to further improve the programmable shader of the combined Rubinstein/Collodi system. A POSITA seeking to enhance the shader’s functionality would have been motivated to incorporate the teachings of Zatz, another reference in the same field concerning programmable shaders. Zatz offered known benefits, such as improved control over the shader and an explicit architecture for multipass rendering, which would have been a desirable feature to add to the combined system.
  • Expectation of Success (for §103 grounds): A POSITA would have expected success in adding Zatz’s features, as Zatz’s programmable shader was designed to be implemented within a graphics pipeline architecture similar to that disclosed by Rubinstein and Collodi.

4. Key Claim Construction Positions

• "Z-Buffer Logic Unit" (Claims 3-5): Petitioner proposed this term be construed as "a logic unit that facilitates visibility testing by comparing depth values." This construction was central to mapping the functionality of Rubinstein's double-z scheme and scan/z engine to the claims.
• "Hierarchical Z-Interface" (Claim 4): Petitioner proposed this term meant "an interface with a z-buffer logic unit that provides for visibility testing at a coarse level, including, for example, for an entire tile or primitive." This construction was used to argue that Rubinstein’s system, which incorporates teachings from related patents on hierarchical z-buffering, met this limitation.
• "Early Z-interface" / "Late Z-interface" (Claims 4-5): Petitioner proposed these terms be construed relative to when visibility testing occurs—either "prior to shading and texturing" (Early Z) or "after shading and texturing" (Late Z). These constructions were critical to arguing that Rubinstein's disclosure of z-buffering both before and after shading satisfied the claim limitations.

5. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial by filing a motion for joinder with IPR2018-00102, an earlier-instituted IPR challenging the same claims of the ’506 patent. Petitioner asserted that the present petition was largely a verbatim copy of the one filed in IPR2018-00102, used the same expert, and was timely filed within one month of the institution decision in that case. Petitioner argued joinder was appropriate to promote efficiency and that the time bar under §315(b) does not apply to a request for joinder.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-9 of the ’506 patent as unpatentable.