PTAB

IPR2018-01249

Apple Inc v. Qualcomm Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Dynamic Word Line Drivers and Decoders for Memory Arrays
  • Brief Description: The ’002 patent describes a wordline driver system for a memory array that reduces power consumption. It achieves this by using a hierarchical decoding scheme with separate first and second logic circuits that decode distinct portions of a memory address to selectively provide a clock signal to only a selected group of wordline drivers.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sato - Claims 1-28 and 31-37 are obvious over Sato.

  • Prior Art Relied Upon: Sato (Patent 4,951,259).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Sato disclosed all limitations of the challenged claims. Sato’s X address decoder (XDCR) was presented as a circuit device with a pre-decoder (PDCR) and decoding NAND gate circuits that function as the claimed “first logic” and “second logic,” respectively. Petitioner asserted Sato’s PDCR receives a timing signal (argued to be equivalent to a clock signal) and a first portion of a memory address (lower 2-bits). The PDCR decodes this address portion to selectively apply the timing signal to one of four outputs connected to a selected group of wordline drivers. The decoding NAND gate circuits receive a second portion of the memory address to activate a particular wordline driver within the selected group.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the argument focused on the motivation to interpret or modify Sato. Petitioner contended a person of ordinary skill in the art (POSITA) would have recognized Sato’s disclosed “timing signal” as being equivalent to a “clock signal” because it performs the same function, is represented by a common symbol for clocks (phi), and Sato explicitly mentioned its invention applies to “clocked static type address decoders.”
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Sato’s circuit uses standard, well-understood components for memory decoding, and interpreting the timing signal as a clock signal involves applying known principles to a conventional circuit architecture.

Ground 2: Obviousness over Asano in view of Itoh - Claims 1-17, 20-28, and 31-36 are obvious over Asano in view of Itoh.

  • Prior Art Relied Upon: Asano (Application # 2006/0098520) and Itoh (Kiyoo Itoh, VLSI Memory Chip Design, Springer 2001).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Asano disclosed the overall architecture of the claimed invention but presented its predecoder as a functional block diagram. Asano's predecoder and Local Clock Buffers (LCBs) were mapped to the "first logic" of claim 1. This logic decodes a first portion of the memory address (the most significant bit) to enable one of the LCBs, which then gates a clock signal to a selected group of wordline drivers. The predecoder and a final decoder in Asano were mapped to the "second logic," which decodes the remaining five address bits to select a specific wordline within the group. Itoh, a standard textbook on memory design, was cited as providing the well-known, conventional circuit implementations (e.g., 1-to-2, 2-to-4, and 3-to-8 decoders) that a POSITA would have used to build the functional blocks described in Asano.
    • Motivation to Combine (for §103 grounds): A POSITA seeking to implement the functional predecoder block shown in Asano would combine its teachings with Itoh's. It was argued that it would be natural and obvious to consult a standard textbook like Itoh for known, off-the-shelf circuit designs to realize the specific decoding functions required by Asano's high-level architecture.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success because the combination merely involved implementing a described function (from Asano) using standard, predictable circuits (from Itoh) for their intended purpose, which is a routine aspect of digital circuit design.

4. Key Claim Construction Positions

  • "static precharge state": Petitioner proposed this term be construed to mean "a state in which a fixed voltage level is applied to a wordline driver." This construction was based on the specification's explicit differentiation between a "dynamic evaluation state" and a "static precharge state (e.g., a fixed voltage level... is applied)." This construction was important for mapping the state of non-selected wordline drivers in the prior art.
  • "conditional clock generator": Petitioner proposed this term be construed as "a circuit component that applies a clock signal to one of several output terminals, selectively." This construction was based on specification language stating the generator "receives a clock signal... and selectively applies the clock signal to a selected one of the clock outputs." This term was central to mapping the function of Sato's PDCR and Asano's LCBs to the claimed invention.

5. Key Technical Contentions (Beyond Claim Construction)

  • Equivalence of "Timing Signal" and "Clock Signal": A central technical contention, particularly for the Sato-based ground, was that a POSITA would have understood the "timing signal (φce)" in Sato to be functionally and structurally equivalent to the claimed "clock signal." Petitioner supported this by noting that: (1) the terms are often used interchangeably in the art; (2) the Greek symbol phi (φ) is conventionally used for clock signals; and (3) Sato’s signal performs the identical function of gating the decoder outputs, a typical role for a clock in synchronous circuits.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-28 and 31-37 of the ’002 patent as unpatentable.