PTAB

IPR2018-01296

Intel Corporation v. VLSI Technology LLC

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1. Case Identification

2. Patent Overview

  • Title: Memory System with Multiple Memory Topologies
  • Brief Description: The ’806 patent discloses a memory system designed to reduce power consumption by using a "first memory" operating at a higher voltage and a "second memory" operating at a lower voltage. This architecture allows the first memory to be placed in a low-power sleep mode while the second memory remains active for certain operations.

3. Grounds for Unpatentability

Ground I: Obviousness over Jouppi, Li, Kojima, and Flautner (Contingent on Petitioner's Claim Construction) - Claims 11-13, 15, and 17 are obvious over Jouppi, Li, Kojima, and Flautner.

  • Prior Art Relied Upon: Jouppi (a 1994 IEEE publication), Li (a 2002 conference proceeding), Kojima (Patent 5,687,382), and Flautner (a 2002 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination renders independent claim 11 and its dependent claims obvious. Jouppi taught the foundational two-level (L1/L2) on-chip cache system, where the L1 cache (the claimed "second memory") used dual-ported SRAM cells and the L2 cache (the "first memory") used single-ported 6T SRAM cells, establishing two memories with different transistor arrangements on a single integrated circuit. Kojima taught using two memories with different minimum operating voltages to reduce power. Li taught a "Speculative-I" method for putting an L2 subblock into a low-power standby mode while the corresponding L1 block remains active, and using a "dirty bit" in L1 as status information to determine when to reactivate L2. Flautner taught a "drowsy cache" technique for reducing leakage in an L2 cache by lowering its supply voltage. For dependent claims, Petitioner argued Li's "normal mode" taught the "active mode" of claim 12; Kojima's separate power supplies for its high- and low-voltage memories taught the separate power supply terminals of claim 13; Jouppi's use of 6T single-ported L2 cells and larger dual-ported L1 cells taught the SRAM topologies with different transistor counts of claim 15; and Li's disclosure of different block sizes for L1 and L2 caches taught that the second memory stores a subset of data from the first memory (claim 17).
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Jouppi with Kojima to reduce power by applying Kojima’s different-voltage memory scheme to Jouppi’s frequently-accessed L1 and larger, less-frequently-accessed L2 caches. A POSITA would then incorporate Li’s "Speculative-I" mechanism, which Li itself noted was applicable to systems like Jouppi’s, to achieve further power savings by placing the L2 cache in standby. Finally, to implement Li's standby mode in a way that aligns with the proposed claim construction, a POSITA would be motivated to use Flautner’s well-known method of lowering the supply voltage, which Li invited by suggesting combination with other leakage-control techniques.
    • Expectation of Success: Petitioner asserted a high expectation of success, as this involved applying known power-saving techniques (Kojima, Li, Flautner) to a standard cache architecture (Jouppi) to achieve the predictable result of reduced power consumption.

Ground II: Obviousness over Jouppi, Li, and Kojima (Alternative Ground) - Claims 11-13, 15, and 17 are obvious over Jouppi, Li, and Kojima.

  • Prior Art Relied Upon: Jouppi (a 1994 IEEE publication), Li (a 2002 conference proceeding), and Kojima (Patent 5,687,382).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative in case the Board did not adopt Petitioner's proposed construction for "second mode of operation." Petitioner argued that the combination of Jouppi, Kojima, and Li alone renders the claims obvious. The mapping of Jouppi (base architecture), Kojima (different operating voltages), and Li (standby modes and status information) is identical to Ground I. This alternative ground also relied on the same combinations for the dependent claims. The key difference is that Flautner is not required, as Petitioner argued that Li's disclosure of a "standby mode" inherently teaches a "second mode of operation" where the first memory is inaccessible while the second is accessible, regardless of the specific voltage implementation.
    • Motivation to Combine: The motivation to combine Jouppi, Kojima, and Li is the same as in Ground I: to improve power efficiency in a standard two-level cache by applying known techniques for differential voltage use and selective standby states to achieve a predictable improvement.
    • Expectation of Success: The expectation of success remained high for the same reasons as in Ground I, as it involved combining complementary and known cache optimization techniques to achieve their intended purpose.

4. Key Claim Construction Positions

  • Term: "second mode of operation" (claim 11)
  • Petitioner's Proposed Construction: "when a lower voltage is provided to the first and second memory."
  • Justification: Petitioner argued this construction was mandated by a clear and unambiguous definitional statement made by the patentee during prosecution of the ’806 patent. When adding the term "second mode of operation" to overcome a rejection, the patentee explained the new limitation in the accompanying remarks by stating: "[T]he second mode of operation (i.e. when a lower voltage is provided to the first and second memory)." Petitioner contended this "i.e." statement acts as a binding definition under both the Broadest Reasonable Interpretation (BRI) and Phillips standards. Petitioner also argued that the claim language and specification support this construction, as they link the second mode to a low-voltage state where the first memory becomes inaccessible while the second, with its lower minimum operating voltage, remains accessible. This construction is central to Ground I, as it directly links the claimed mode to the physical act of lowering voltage, making Flautner's teachings on "drowsy" (low-voltage) caches directly relevant.

5. Arguments Regarding Discretionary Denial

  • Petitioner acknowledged the existence of a co-pending inter partes review (IPR) against the same ’806 patent (IPR2018-01034). However, Petitioner argued against discretionary denial of the instant petition. The core reason provided was that this petition was filed over a month before the Patent Owner's Preliminary Response was due in the first IPR. Petitioner contended this timing provided the Board with sufficient opportunity to evaluate the petition's merits without causing undue prejudice to the Patent Owner or creating significant inefficiency.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 11-13, 15, and 17 of the ’806 patent as unpatentable under 35 U.S.C. §103.