PTAB

IPR2018-01296

Intel Corp v. VLSI Technology LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Dual-Memory System for Power Reduction
  • Brief Description: The ’806 patent discloses a memory system on an integrated circuit designed to reduce power consumption. The system uses a "first memory" operating at a higher voltage and a "second memory" operating at a lower voltage, allowing the first memory to enter a low-power sleep mode while the second remains active and accessible.

3. Grounds for Unpatentability

Ground I: Obviousness over Li, Jouppi, Kojima, and Flautner (Conditional on Claim Construction) - Claims 11-13, 15, and 17 are obvious over Li, Jouppi, Kojima, and Flautner if Petitioner’s proposed construction of “second mode of operation” is adopted.

  • Prior Art Relied Upon: Li (a 2002 conference proceeding, "Leakage Energy Management in Cache Hierarchies"), Jouppi (an IEEE 1994 publication, "Tradeoffs in Two-Level On-Chip Caching"), Kojima (Patent 5,687,382), and Flautner (an IEEE 2002 publication, "Drowsy Caches: Simple Techniques for Reducing Leakage Power").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of references taught every limitation of the challenged claims. Jouppi was argued to disclose the foundational two-level (L1/L2) on-chip cache architecture, with a "first memory" (L2) and "second memory" (L1) having different memory cell topologies (single-ported vs. dual-ported SRAMs). Kojima was asserted to teach using memory cells with different minimum operating voltages in the same system to reduce power, specifically using lower-voltage cells for more frequently accessed memory. Li allegedly disclosed the claimed modes of operation by teaching a "standby mode" for an L2 cache subblock (making it inaccessible) while the corresponding L1 block remains active. Li also taught using "dirty bit" status information in the L1 block to trigger reactivation of the L2 subblock. Finally, Flautner was argued to teach the implementation of this standby mode by lowering the supply voltage to the L2 cache, placing it in a "drowsy" state, which aligns with Petitioner's proposed claim construction.
    • Motivation to Combine: A POSITA would combine these known techniques to improve the power efficiency of Jouppi's standard two-level cache architecture. A POSITA would apply Kojima's voltage-differentiation strategy to reduce dynamic power in the frequently accessed L1 cache. To address static leakage in the larger L2 cache, a POSITA would incorporate the "standby mode" taught by Li. Because Li expressly suggests using other leakage-control mechanisms and references Flautner, a POSITA would be motivated to implement Li's standby mode using Flautner's well-known "drowsy cache" technique of lowering the supply voltage.
    • Expectation of Success: Petitioner asserted a high expectation of success because the combination involved applying established and compatible power-saving techniques to a conventional cache architecture to achieve the predictable result of reduced power consumption.

Ground II: Obviousness over Li, Jouppi, and Kojima (Alternative Ground) - Claims 11-13, 15, and 17 are obvious over Li, Jouppi, and Kojima if Petitioner’s proposed construction is not adopted.

  • Prior Art Relied Upon: Li (a 2002 conference proceeding, "Leakage Energy Management in Cache Hierarchies"), Jouppi (an IEEE 1994 publication, "Tradeoffs in Two-Level On-Chip Caching"), and Kojima (Patent 5,687,382).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative, arguing that even without Flautner, the combination of Jouppi, Kojima, and Li renders the claims obvious. The mapping for these three references is identical to Ground I. Petitioner argued that Li's disclosure of a "standby mode"—where the L2 subblock is inaccessible while the L1 block remains active—is itself a "second mode of operation" distinct from the "normal mode" where both are active. Therefore, a specific teaching of lowering voltage (from Flautner) was not essential if the claim term was construed more broadly as simply a different mode of operation.
    • Motivation to Combine: The motivation remained the same as in Ground I: to improve the power efficiency of the Jouppi cache architecture. A POSITA would still be motivated to combine Kojima's voltage optimization with Li's standby mode and status bit functionality to reduce both dynamic and static power consumption.
    • Expectation of Success: Success was expected for the same reasons as Ground I, as the combination still involved applying known and compatible techniques to a standard device to achieve a predictable improvement.

4. Key Claim Construction Positions

  • "second mode of operation": Petitioner argued this term, central to claim 11, should be construed to mean "when a lower voltage is provided to the first and second memory."
    • This proposed construction was based on what Petitioner characterized as an explicit definition provided by the patentee during prosecution of the ’806 patent. The patentee allegedly used the phrase "i.e." to define the term in an amendment, creating a clear and unambiguous statement of its meaning. This construction is critical as it directly supports the inclusion of Flautner's teachings of lowering supply voltage in Ground I.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial based on a previously filed IPR petition (IPR2018-01034) against the same patent.
    • Petitioner contended that at the time of filing this second petition, the Patent Owner had not yet submitted its preliminary response in the first proceeding, and over a month remained before that deadline. This timing was presented as a significant factor weighing against discretionary denial, consistent with PTAB guidance in cases like General Plastic.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 11-13, 15, and 17 of the ’806 patent as unpatentable.