PTAB

IPR2018-01315

Apple Inc v. Qualcomm Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multiple Supply-Voltage Power-Up/Down Detectors
  • Brief Description: The ’674 patent relates to a power-on/off-control (POC) circuit for integrated circuits that use multiple supply voltages (e.g., a low-voltage core and a high-voltage I/O). The circuit is designed to detect when the core network powers down and transmit a control signal to prevent the I/O network from processing and transmitting erroneous signals that can occur during such power-down states.

3. Grounds for Unpatentability

Ground 1: Obviousness over Steinacker, Doyle, and Park - Claims 1, 2, and 5-7 are obvious over Steinacker in view of Doyle and Park.

  • Prior Art Relied Upon: Steinacker (Patent 7,279,943), Doyle (Patent 4,717,836), and Park (a 2006 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Steinacker taught a circuit for multi-voltage systems that uses a voltage level detector to ensure reliable operation, and suggested this detector could be an inverter. Doyle disclosed an improved CMOS inverter with a feedback network and processing stages nearly identical to the circuit claimed in the ’674 patent. Park taught that "transistor stacking"—replacing a single transistor with two stacked transistors—was a well-known technique to reduce leakage current in inverters. The combination of these references allegedly disclosed every limitation of the challenged claims, with Park’s teaching resulting in the specific multi-transistor power-up/down detector structure recited in the claims.
    • Motivation to Combine: A POSITA, seeking to implement the inverter-based voltage detector suggested by Steinacker, would combine it with Doyle’s stable and improved inverter design. To address the known issue of leakage current, the POSITA would then have been motivated to apply the conventional transistor stacking technique taught by Park to Doyle’s inverter. This combination represented a simple substitution of known elements to achieve predictable results.
    • Expectation of Success: Petitioner asserted that a POSITA would have had a high expectation of success, as the combination involved applying known design improvements (a stable inverter, leakage reduction techniques) to a known type of circuit (a voltage detector) to solve a known problem.

Ground 2: Obviousness over Admitted Prior Art and Majcherczak - Claims 1, 2, 5, and 6 are obvious over Applicant's Admitted Prior Art (AAPA) in view of Majcherczak.

  • Prior Art Relied Upon: AAPA (disclosed in the ’674 patent’s background and FIG. 1) and Majcherczak (Application # 2002/0163364).
  • Core Argument for this Ground:
    • Prior Art Mapping: The AAPA, taken from the ’674 patent itself, described a standard POC system that included a power-up/down detector and processing circuitry but lacked the claimed feedback circuit. Majcherczak addressed the same technical problem and explicitly taught a voltage detector that included a feedback transistor (M6) to provide “proper stabilizing” of the circuit and create hysteresis. Petitioner argued that adding Majcherczak’s feedback transistor in parallel with the detector’s pull-up transistor in the AAPA circuit would result in the circuit of the ’674 patent, where the feedback adjusts the detector’s current capacity.
    • Motivation to Combine: A POSITA would combine the references to improve the performance of the standard AAPA circuit. Majcherczak expressly taught using a feedback transistor to enhance stability and add hysteresis to a nearly identical circuit, providing a clear motivation to incorporate this feature into the AAPA’s POC system to gain these known benefits.
    • Expectation of Success: The combination involved integrating a known feature from one voltage detection circuit into another functionally commensurate circuit to achieve a predictable improvement. Therefore, a POSITA would have had a reasonable expectation of success.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 7 based on AAPA, Majcherczak, and Matthews (Patent 6,646,844). This ground relied on the same core combination as Ground 2, with Matthews added to provide the express motivation for incorporating the resulting semiconductor die into devices such as a mobile phone or computer system, as recited in claim 7.

4. Key Claim Construction Positions

  • Petitioner argued the term "processing circuitry" from claim 1 should be construed to encompass, at a minimum, an amplifying inverter. This construction was based on the ’674 patent’s explicit description of the "signal processor" component of the processing circuitry as comprising an inverting amplifier in its disclosed embodiments. This construction was central to mapping the inverter-based signal processing stages of the prior art references to this claim limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claims 1, 2, and 5-7 of the ’674 patent as unpatentable.