PTAB

IPR2018-01406

Intel Corp v. Godo Kaisha IP Bridge 1

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device
  • Brief Description: The ’409 patent relates to semiconductor devices and their fabrication methods, purporting to solve problems with over-etching during the manufacturing process. The disclosed solution involves an isolation structure having a top surface at a higher level than the surface of the adjacent active device area.

3. Grounds for Unpatentability

Ground 1: Claims 1, 6-8, 12, 15, 18, 21, 24, 28, 31, 35, 39, 40, 44, 47, 51, 55, and 60 are obvious over Cederbaum.

  • Prior Art Relied Upon: Cederbaum (Patent 5,275,963).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Cederbaum, which was not considered during prosecution, teaches a semiconductor device structure that renders the challenged claims obvious. Cederbaum discloses a device with a semiconductor substrate, an active region (21), and an isolating field recess oxide (ROX) region (20). It further shows an interconnection (polysilicon line 23-1) formed on the ROX isolation, an insulating film (PSG layer 26) over the interconnection, and a hole (28-1) formed through the insulating layers to expose both the active region and the interconnection. A conductive layer (tungsten plug 30-1 and Ti/TiN film 29-1) fills this hole, connecting to an upper interconnection member (resistive polysilicon land 31-1). Petitioner contended this structure maps directly to the limitations of independent claim 1 and its dependents.
    • Motivation to Combine (for §103 grounds): This ground is based on a single reference. However, Petitioner argued that to the extent the term "interconnection member" requires a low-resistance conductor, a person of ordinary skill in the art (POSITA) would have been motivated to modify Cederbaum’s resistive polysilicon land (31-1). Cederbaum explicitly teaches that its polysilicon lands can be processed to be either resistive or highly conductive. A POSITA would have found it obvious to use the conductive variant to simplify the manufacturing process and reduce masking complexity, a well-known goal in the industry.
    • Expectation of Success (for §103 grounds): Because Cederbaum itself provides the alternative processing steps to make the polysilicon lands conductive, a POSITA would have had a high expectation of success in making this modification without disrupting the device's function.

Ground 2: Claims 2-5, 9-11, 13-14, 16-17, 19-20, and 22-23 are obvious over Cederbaum in view of Lee.

  • Prior Art Relied Upon: Cederbaum (Patent 5,275,963) and Lee (Patent 4,952,524).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targets dependent claims that specifically require the isolation to be a "trench isolation." Petitioner argued that Cederbaum's disclosure of a Local Oxidation of Silicon (LOCOS) based ROX isolation meets all other limitations of the base claims. Lee was introduced for its explicit teaching of using trench isolation, specifically a raised trench isolation structure where the top surface protrudes above the silicon wafer surface. Petitioner contended that substituting Cederbaum’s LOCOS isolation with Lee’s superior raised trench isolation renders the claims obvious.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Cederbaum and Lee as both references are in the same field of semiconductor manufacturing and share the common goal of device miniaturization. Petitioner asserted that at the time of the invention, there was a strong, well-documented industry trend of replacing older LOCOS technology with more space-efficient Shallow Trench Isolation (STI) technology. Lee explicitly teaches that trench isolation consumes less space and avoids the performance-degrading "bird's beak" effect inherent to LOCOS structures like Cederbaum's ROX, providing a clear reason to make the substitution.
    • Expectation of Success (for §103 grounds): The replacement of LOCOS with trench isolation was a well-known, conventional process modification in the semiconductor industry. A POSITA would have recognized it as a suitable replacement technology with predictable and well-understood benefits, leading to a reasonable expectation of success.

4. Key Claim Construction Positions

  • Petitioner argued that the claim term "formed on" should be construed as "formed directly or indirectly on," consistent with an agreement between the parties in a related district court litigation. This construction was critical to Petitioner's argument that Cederbaum’s insulating phosphosilicate glass (PSG) layer (26) meets the claim limitation of being "formed on" an interconnection, even though an etch stop layer (25) and a diffusion barrier layer are located between the PSG layer and the interconnection.

5. Key Technical Contentions (Beyond Claim Construction)

  • Obvious Substitution of Isolation Technologies: A central technical contention was that replacing the LOCOS isolation in Cederbaum with the advanced trench isolation taught by Lee was not an inventive step but a simple substitution of an old technology for a newer, known-superior one. Petitioner framed this as an obvious design choice for any POSITA seeking to improve device density and performance, consistent with the industry's direction at the time.
  • Interchangeability of Polysilicon Properties: Petitioner contended that modifying a polysilicon layer to be either resistive or conductive was a routine, well-understood technique. The argument was that since Cederbaum itself taught processes for both types, choosing the conductive variant to meet a claim limitation was merely taking advantage of a known, available option for a predictable result.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-24, 28, 31, 35, 39, 40, 44, 47, 51, 55, and 60 of the ’409 patent as unpatentable.