PTAB

IPR2018-01410

Samsung Electronics Co Ltd v. BiTMICRO LLC

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petition

1. Case Identification

2. Patent Overview

  • Title: Flash Memory Systems
  • Brief Description: The ’416 patent relates to flash memory systems intended to improve operational speed. The invention purports to overcome the inherent slowness of flash erase operations by performing multiple erase cycles as a group in parallel before executing subsequent write cycles, and it utilizes a write cache to manage write operations.

3. Grounds for Unpatentability

Ground 1: Claims 1-20 are obvious over Harari in view of Sukegawa.

  • Prior Art Relied Upon: Harari (Patent 5,535,328) and Sukegawa (Patent 5,572,466).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Harari discloses the core elements of the challenged claims, including a flash memory system with a cache and a controller that detects when cache entries need to be written to memory. Harari further teaches a "multiple sector erase" process where numerous memory sectors can be erased simultaneously to accommodate new data. While Harari discloses parallel erasing, Petitioner contended that Sukegawa explicitly teaches a memory system designed for parallel access across multiple flash EEPROM chips, including performing both erase and subsequent write operations in parallel to improve system throughput. The combination, therefore, provides for performing a plurality of erase operations followed by a plurality of sequential write operations, all in parallel, as required by the claims.
    • Motivation to Combine: A POSITA would combine Sukegawa’s parallel architecture with Harari’s flash memory system to achieve Harari's express goal of creating a "faster and more efficient" device. Sukegawa’s teachings on parallel writes were a known method for improving the performance of flash memory systems like the one described in Harari.
    • Expectation of Success: Petitioner asserted that a POSITA would have a reasonable expectation of success in combining these references. The predictable nature of flash memory controllers and the high level of implementation detail provided in both Harari and Sukegawa would make the integration straightforward.

Ground 2: Claims 1-20 are obvious over Suzuki in view of Sukegawa.

  • Prior Art Relied Upon: Suzuki (Patent 6,526,472) and Sukegawa (Patent 5,572,466).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Suzuki discloses a file management system for flash memory that uses a buffer cache to temporarily store data. Suzuki’s system detects and flushes "dirty" cache entries to the main flash memory when the cache fills up or during periodic "sync processing." Erase operations occur either to overwrite a specific block or as part of a "garbage collection" routine to free up space. Petitioner argued that while Suzuki provides the caching and data management logic, it lacks an explicit parallel, multi-chip architecture. Sukegawa supplies this element by teaching a system that uses multiple flash chips operating in parallel for both erase and write operations to increase performance.
    • Motivation to Combine: A POSITA would be motivated to implement Sukegawa's parallelism in Suzuki's system because both references are focused on the same technical problem: using flash memory to replace slower mechanical hard drives in the "semiconductor disk drive" market. In this context, parallelism is a well-known and critical technique for achieving necessary performance levels.
    • Expectation of Success: Petitioner argued the combination was particularly amenable and success would be expected. Both Suzuki and Sukegawa utilize virtual addressing schemes to manage the flash memory, making their respective techniques highly compatible for integration by a POSA. Implementing Sukegawa's parallel hardware architecture would be a logical and predictable way to enhance the performance of Suzuki's file management system.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of Patent 6,529,416 as unpatentable.