PTAB

IPR2018-01411

Samsung Electronics Co Ltd v. BiTMICRO LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Flash Memory Systems
  • Brief Description: The ’416 patent discloses flash memory systems and methods designed to improve performance by overcoming the slow speed of erase operations. The invention claims to reduce total write transaction time by performing erase operations for a plurality of memory locations in parallel before performing a subsequent plurality of sequential write operations to those locations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Nishikawa - Claims 1-2, 5-7, 10-12, 15-17, and 20 are obvious over Nishikawa.

  • Prior Art Relied Upon: Nishikawa (European Patent Application Publication No. 0649095A2).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Nishikawa, which was not considered during prosecution, teaches all limitations of the challenged independent and dependent claims. Nishikawa discloses a flash memory system with a cache that improves performance through parallelism. Specifically, Nishikawa’s control unit 3, which includes a block selection unit 34 and combination determination unit 127, detects a plurality of dirty cache entries that need to be written to the flash memory array. Its erasure control unit 125 then proactively and concurrently erases a portion of the memory (three data blocks) to accommodate writing these entries. Subsequently, when write commands for these entries are received, Nishikawa’s arbitrator 38 writes the data to the pre-erased blocks. Petitioner asserted this sequence meets the core limitations of detecting entries, erasing a portion of memory for them, and then writing them.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the motivation was inherent in Nishikawa's own disclosure. Petitioner contended Nishikawa explicitly teaches using these parallel operations to solve the same problem as the ’416 patent: overcoming the delay caused by slow erase operations in flash memory. A person of ordinary skill in the art (POSITA) would have recognized that implementing Nishikawa's disclosed parallel erasure and subsequent writing would result in the claimed invention.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because Nishikawa provides a detailed description of the circuitry and control flow for implementing its parallel processing, demonstrating its workability.

Ground 2: Obviousness over Nishikawa in view of Sukegawa - Claims 1-20 are obvious over Nishikawa in view of Sukegawa.

  • Prior Art Relied Upon: Nishikawa (European Patent Application Publication No. 0649095A2) and Sukegawa (Patent 5,572,466).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground primarily addressed dependent claims reciting the processing of a "second plurality of entries" in parallel with the first. Petitioner argued that Nishikawa teaches the fundamental system for processing a first plurality of entries in parallel. Sukegawa explicitly teaches extensive parallelism in flash memory systems to improve performance, particularly for the semiconductor disk drive market. Sukegawa shows multiple flash EEPROM chips being erased and written to in parallel, with each parallel operation involving multiple sequential writes. Petitioner asserted that combining these teachings renders all claims obvious. The combination would involve duplicating Nishikawa's already-parallel processing components to handle a second set of dirty cache entries simultaneously, as suggested by the broad parallel architecture in Sukegawa.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Nishikawa and Sukegawa to further improve system performance, a primary goal in memory design. Nishikawa already provided a foundation for parallel processing on its multiple independent memory chips. Sukegawa demonstrated the known benefits of expanding such parallelism across more chips and operations to increase speed and efficiency. The motivation was to apply Sukegawa’s teachings on broad parallelism to Nishikawa’s more specific cache management system to achieve even faster access times.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because the combination involves the mere duplication of parts (Nishikawa's processing logic) to perform identical functions in parallel, a predictable and well-established engineering practice reinforced by Sukegawa's teachings.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’416 patent as unpatentable.