PTAB

IPR2018-01486

Intel Corp v. Godo Kaisha IP Bridge 1

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Device and Method of Manufacturing the Same
  • Brief Description: The ’165 patent describes a three-dimensional semiconductor device, such as a FinFET transistor, featuring a semiconductor "fin" with upper and side portions. The purported novelty is that the resistivity of an impurity region in the side portion is substantially equal to or smaller than the resistivity of an impurity region in the upper portion, which allegedly improves transistor performance.

3. Grounds for Unpatentability

Ground 1: Claims 1-11 are obvious over Doyle ’862 in combination with Doyle ’373.

  • Prior Art Relied Upon: Doyle ’862 (Patent 7,494,862) and Doyle ’373 (Patent 7,449,373).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Doyle ’862 teaches a method for achieving "uniform doping of non-planar transistor structures" like FinFETs. This process involves separate vertical ion implantation for the top surface of the fin and angled ion implantation for the side surfaces, resulting in a fin that is "uniformly doped." Petitioner contended that a person of ordinary skill in the art (POSITA) would understand that uniform doping directly results in the uniform resistivity claimed in the ’165 patent, as resistivity is a direct function of dopant concentration. Doyle ’373 was cited for its well-known teachings on implanting specific regions of a FinFET, such as the "tip implant" or extension regions, to optimize performance and reduce short-channel effects. Dependent claims were argued to recite conventional FinFET features also disclosed or rendered obvious by the combination, such as the fin shape (claim 3), gate insulating films (claim 5), and sidewall spacers (claim 8).
    • Motivation to Combine: A POSITA would combine these references because both addressed the common problem of optimizing doping in 3D transistors to enhance performance. Doyle ’862 focused on uniform doping of the main source-drain regions, while Doyle ’373 provided specific techniques for doping the extension regions. Petitioner asserted a POSITA would have been motivated to combine the distinct but complementary doping methods for different parts of the transistor to fabricate a device with overall optimal characteristics. The motivation was further supported by the fact that both patents share inventors and were assigned to the Petitioner, Intel Corporation.
    • Expectation of Success: Combining the known doping processes from Doyle ’862 and Doyle ’373 would have yielded the predictable result of a uniformly doped transistor with improved performance, as both were established steps in semiconductor fabrication.

Ground 2: Claims 1, 3-12 are obvious over Goktepeli in combination with Doyle ’373.

  • Prior Art Relied Upon: Goktepeli (Patent 7,323,389) and Doyle ’373 (Patent 7,449,373).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Goktepeli discloses an alternative method for achieving uniform doping that also renders the claims obvious. Goktepeli teaches forming a "sacrificial doping layer" over the FinFET structure. Upon heating (annealing), dopants from this layer "evenly and thoroughly diffuse" into the source-drain regions of the fin. Petitioner contended this even diffusion process would inherently result in a uniform dopant concentration across the upper and side surfaces of the fin, thereby achieving the claimed resistivity relationship. As in Ground 1, Doyle ’373 was used to supply the conventional technique of using angled ion implantation to form the extension regions. Dependent claims were addressed similarly, arguing Goktepeli taught or suggested the recited conventional FinFET features.
    • Motivation to Combine: A POSITA would combine Goktepeli and Doyle ’373 to create a FinFET with desirable characteristics. Goktepeli teaches using diffusion from a sacrificial layer to achieve a uniformly doped source-drain region, which reduces parasitic resistance. Doyle ’373 teaches using angled ion implantation to dope the extension regions to mitigate short-channel effects. Petitioner argued a POSITA would have been motivated to combine these two known techniques to create a transistor with both uniformly doped source-drain regions and properly formed extension regions, leading to predictable improvements in overall device performance.
    • Expectation of Success: The combination involved applying known doping methods to different, distinct regions of the transistor (source-drain and extension regions), which a POSITA would have reasonably expected to result in a functional, high-performance device.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-12 of Patent 7,800,165 as unpatentable.