PTAB

IPR2018-01545

Samsung Electronics Co Ltd v. BiTMICRO LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Module with Serial Chain Routing
  • Brief Description: The ’103 patent relates to a method for stacking multiple chip modules (MCMs) to increase memory density and support miniaturization. The challenged claims are directed to an embodiment that uses serial chain routing to connect signals through all modules in a stack, analogous to a JTAG (Joint Test Action Group) daisy-chain configuration for testing.

3. Grounds for Unpatentability

Ground 1: Claims 12 and 16 are obvious over Sato

  • Prior Art Relied Upon: Sato (International Publication No. WO 2004/072667).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sato disclosed all elements of the challenged claims. Sato taught a stack of memory modules capable of performing a vertical JTAG boundary scan across all modules using a "daisy chain" configuration. Petitioner asserted that Sato’s "connection terminals" functioned as the claimed active ports and its "penetrating electrodes" functioned as the claimed passive ports, which pass signals between stacked modules. Sato’s TDI/TDO daisy chain was mapped to the "first serial chain route," while a separate TDO2 signal path was mapped to the "second serial chain route." Petitioner further argued that Sato’s control circuitry (a tri-state buffer and comparison means) in the uppermost ("end") module determined its position in the stack and enabled a routing path connecting the first and second serial chains, meeting the final limitations of independent claim 12. For dependent claim 16, Petitioner contended that each of Sato’s stacked modules contained a boundary scan controller and could therefore be considered a "controller module."

Ground 2: Claims 12 and 16 are obvious over Sato in view of Gaynes

  • Prior Art Relied Upon: Sato (WO 2004/072667) and Gaynes (Patent 6,236,115).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground reinforced the arguments made against Sato, anticipating a potential argument from the Patent Owner that Sato’s connections do not explicitly disclose the "ball and pad" structures described in the ’103 patent. Sato provided the foundational architecture of stacked memory modules with JTAG daisy-chain routing. Gaynes was cited for its disclosure of a method for forming interconnections in stacked memory modules using thru-silicon vias (TSVs) with conductive pads and solder balls. Petitioner argued that Gaynes’s surface deposits (pads) and metallization-filled TSVs (passive ports) taught the claimed active and passive port structures.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) reading Sato, which does not specify the materials or precise structure for its connections, would have been motivated to look to well-known prior art like Gaynes for implementation details. Gaynes offered a known, advantageous method for creating robust electrical connections between stacked chips, providing benefits such as enhanced durability, noise immunity, and improved performance.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because both references addressed the same technical problem of interconnecting stacked memory chips. Gaynes’s TSV and ball/pad structures served the same function as Sato’s penetrating electrodes and connection terminals, making the combination a predictable application of known elements to yield improved results.

Ground 3: Claims 12 and 16 are obvious over Sung in view of Funaba

  • Prior Art Relied Upon: Sung (Application # 2003/0178228) and Funaba (Application # 2005/0082664).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Sung disclosed a general architecture for three-dimensional stacked integrated circuits that met the claim limitations, while Funaba provided the motivation to apply it specifically to memory modules. Sung taught stacking identical dies with vertical conductors (through-vias and solder mounds) and terminators (3D via pads) that established serial communication paths. Petitioner mapped Sung's "inter-die scan chain" to the claimed "first serial chain route" and its "broadcasting circuit" to the "second serial chain route." Sung also disclosed a control circuit (a "die identifier circuit" and a "tristate buffer") in the bottom module—an "end module"—that enabled a routing path between the two serial routes based on a control signal indicating its position at the bottom of the stack.
    • Motivation to Combine: A POSITA would combine Sung's general stacking architecture with Funaba's specific teachings on stacked memories to achieve the known benefits of 3D stacking, such as increased data storage density and performance, without incurring extra design effort. Because both references described stacking identical layers for similar purposes, their teachings were compatible and complementary.
    • Expectation of Success: Both references operated in the same technical field, and applying Sung’s communication and control architecture to Funaba’s stacked memory modules would have been a predictable integration. For dependent claim 16, Petitioner argued it would have been obvious to mount the stacked memory system on a memory controller, as taught by Funaba, which would function as the claimed "controller module."

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 12 and 16 based on Sato in view of Eide (Patent 5,612,570). This combination was presented to counter any potential argument that the term "memory module" required a semiconductor chip mounted on a PCB substrate, a structure explicitly taught by Eide.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 12 and 16 of the ’103 patent as unpatentable.