PTAB

IPR2018-01601

Microsoft Corp v. Saint Regis Mohawk Tribe

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multi-Adaptive Processing Systems and Techniques for Enhancing Parallelism and Performance of Computational Functions
  • Brief Description: The ’324 patent describes a method for data processing in a reconfigurable computing system, such as one using Field Programmable Gate Arrays (FPGAs). The claimed method uses systolic processing to simultaneously handle different "data dimensions" of a calculation via "systolically linked lines of code" instantiated as clusters of functional units.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claim 1 is anticipated by Splash2.

  • Prior Art Relied Upon: Splash2 (a 1996 book titled "Splash 2: FPGAs in a Custom Computing Machine").
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the Splash2 reference described a complete, real-world implementation of the method claimed in claim 1. The Splash 2 system was a reconfigurable computer using FPGAs that implemented systolic array architectures to perform high-speed comparisons of genetic sequences. Petitioner mapped each limitation of claim 1 to the Splash 2 disclosure: the system transformed an "Edit Distance Algorithm" into a hardware configuration ("calculation") that was "systolically implemented" on its reconfigurable processors. The Processing Elements (PEs) in Splash2's arrays were the claimed "functional units," which were instantiated to perform the calculation. The system operated on different "data dimensions" (e.g., different time steps of character comparisons) concurrently across multiple PEs, with data passed "seamlessly" between them. The systolic operation was "transport triggered" by the arrival of data, and the reference's silence on a driving clock or program counter was argued to satisfy this negative limitation.

Ground 2: Obviousness - Claims 8 and 9 are obvious over Splash2 in view of RaPiD.

  • Prior Art Relied Upon: Splash2 (1996 book) and RaPiD (a 1997 IEEE paper on a reconfigurable pipelined datapath).
  • Core Argument for this Ground:
    • Prior Art Mapping: Claims 8 and 9 add the limitation that the calculation of claim 1 comprises a JPEG or MPEG image compression, respectively. Petitioner contended that RaPiD taught implementing a 2-D Discrete Cosine Transform (DCT)—the core computational block for both JPEG and MPEG compression—on a systolic array within a reconfigurable computing system. The petition argued that the functionality of a processing cell in RaPiD's DCT array was analogous to the operation of a PE in Splash2's unidirectional systolic array. Combining the teachings would result in a system where Splash2's hardware performs the DCT calculation taught by RaPiD, thereby satisfying all limitations of claims 1, 8, and 9.
    • Motivation to Combine: A POSITA would combine these references as both addressed high-performance parallel processing on reconfigurable hardware. RaPiD expressly cited the Splash 2 system as a "very successful example" of a reconfigurable computer, providing a direct motivation to implement advanced algorithms like DCT on the Splash 2 platform. Furthermore, applying popular and computationally intensive image compression techniques to a powerful, known hardware platform would have been a logical and predictable step to improve performance.
    • Expectation of Success: A POSITA would have a high expectation of success, as both systems used analogous architectures (systolic arrays on FPGAs) to achieve similar goals of high-throughput computation.

Ground 3: Obviousness - Claim 20 is obvious over Splash2 in view of Jeong.

  • Prior Art Relied Upon: Splash2 (1996 book) and Jeong (a 1997 IEEE paper on VLSI arrays for RSA modular multiplication).

  • Core Argument for this Ground:

    • Prior Art Mapping: Claim 20 adds the limitation that the calculation of claim 1 comprises an "encryption algorithm." Petitioner asserted that Jeong disclosed a systolic implementation of a modular multiplication algorithm, a key component of RSA encryption, and explicitly stated its suitability for implementation on FPGAs. Petitioner argued it would have been obvious to implement Jeong's encryption algorithm on the Splash 2 hardware platform, creating a system that meets the limitations of claims 1 and 20. The processing nodes in Jeong's three-level systolic array would map to the "functional units" instantiated on the Splash 2 system.
    • Motivation to Combine: A POSITA would be motivated to combine the references to achieve hardware-accelerated encryption, a well-established goal by the patent's priority date. Jeong provided the systolic algorithm suitable for FPGAs, and Splash2 provided a proven, high-performance FPGA-based systolic processing platform. The combination represented a straightforward application of a known algorithm to a known, compatible system to achieve predictable performance benefits.
    • Expectation of Success: Success would be highly expected, as Jeong's disclosure that its algorithm was designed for implementation in FPGAs directly aligned with the FPGA-based architecture of the Splash 2 system.

  • Additional Grounds: Petitioner asserted alternative obviousness challenges for claim 1, arguing it was obvious over Splash2 alone and over Splash2 in view of Gaudiot (a 1987 paper on data-driven computers).

4. Key Claim Construction Positions

  • "systolic": This was the most critical term. Petitioner argued, based on statements made by the patentee during prosecution, that the term should be construed to mean "the characteristic of rhythmically computing and passing data directly between processing elements 'without a program counter or clock that drives the movement of data' and operating in a manner that is 'transport triggered, i.e., by the arrival of a data object.'" This construction's negative limitation ("without a program counter or clock") was central to the petitioner's argument that Splash2's silence on this point satisfied the claim element for anticipation.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 8, 9, and 20 of Patent 7,225,324 as unpatentable.