PTAB

IPR2019-00022

Samsung Electronics Co., Ltd. v. Invensas Bonding Technologies, Inc.

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1. Case Identification

2. Patent Overview

  • Title: Method for Low Temperature Direct Bonding Using an Etching Process
  • Brief Description: The ’505 patent discloses a method for bonding semiconductor wafers at low or room temperature. The method involves forming and planarizing a bonding layer, slightly etching the layer to activate the surface, terminating the activated surface with a desired chemical species, and then bonding it to another surface to achieve a high-strength bond.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harendt and Yamagata - Claims 77, 79, 80-82, 93-95, 104, 110-114, 192, and 197 are obvious over Harendt in view of Yamagata.

  • Prior Art Relied Upon: Harendt (C. Harendt, Vertical Polysilicon Interconnects by Aligned Wafer Bonding, 1998) and Yamagata (Japan Patent Application Publication No. H7-249749).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Harendt discloses the fundamental bonded structure recited in independent claims 77 and 192, including a processed semiconductor wafer with CMOS circuitry and a planarized insulating layer (a plasma-deposited oxide layer). However, Harendt uses a high-temperature anneal. Petitioner asserted that Yamagata teaches the missing element: a low-temperature bonding method using a plasma treatment (e.g., with hydrogen, oxygen, or nitrogen, including ammonia) to etch, activate, and terminate the bonding surface. Yamagata's process creates a strong bond at temperatures of 200°C or lower, suitable for structures with temperature-sensitive components like those in Harendt. Dependent claims were argued to be obvious as they recite well-known features, such as the use of CMOS circuits (Harendt), deposited silicon oxide (Harendt's TEOS layer), and nitrogen-based termination species (Yamagata's ammonia plasma).
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) building the vertically integrated image sensor of Harendt would have been motivated to improve the bonding process. Harendt's goal of avoiding voids and Yamagata's disclosure of using plasma treatment to create strong, low-temperature bonds with few voids would have provided a clear reason to combine the teachings. Both references operate in the same field of direct wafer bonding for silicon-on-insulator (SOI) structures, making the combination straightforward.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining the references involved applying Yamagata’s known plasma activation technique to Harendt’s known semiconductor structure to achieve the predictable benefit of a strong, low-temperature bond.

Ground 2: Obviousness over Harendt, Yamagata, and Tong - Claims 84, 105, and 106 are obvious over Harendt and Yamagata in view of Tong.

  • Prior Art Relied Upon: Harendt, Yamagata, and Tong (Q. Tong et al., Semiconductor Wafer Bonding: Recent Developments, 1994).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the combination of Harendt and Yamagata from Ground 1. Petitioner argued that the additional limitations in claims 84, 105, and 106 are taught by Tong. Specifically, claim 84 requires thinning the silicon substrate. Petitioner asserted that Tong explicitly teaches that "gaps can be more easily closed for thinner wafers" during bonding, providing a direct motivation to thin the CMOS substrate of Harendt to achieve a stronger bond. Claim 105 requires the oxide layer to be a "native oxide layer." Tong was cited for disclosing the common practice of bonding wafers with native oxide surfaces, making this an obvious and well-understood alternative to Harendt's deposited oxide.
    • Motivation to Combine: A POSITA, having combined Harendt and Yamagata, would have consulted a general survey reference like Tong to optimize the bonding process. Tong's teachings on wafer thinning and the use of native oxides were presented as well-known methods to improve bond strength and simplify manufacturing, providing a clear motivation for their incorporation.
    • Expectation of Success: The combination was argued to be predictable. Applying Tong's conventional techniques (wafer thinning, using native oxide) to the Harendt/Yamagata process would predictably result in a stronger bond, a well-understood outcome in the art.

Ground 3: Obviousness over Harendt, Yamagata, and Bower - Claims 99-101 are obvious over Harendt and Yamagata in view of Bower.

  • Prior Art Relied Upon: Harendt, Yamagata, and Bower (Patent 5,503,704).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground also builds on the Harendt and Yamagata combination. It addresses claims 99 and 100, which require the etched surface to have a specific RMS surface roughness (0.1-3.0 nm and 0.5-1.0 nm, respectively). Petitioner argued that while Yamagata teaches a controlled etch to avoid excessive roughness, Bower provides the explicit disclosure for this limitation. Bower teaches a low-temperature nitrogen bonding process using ammonia plasma activation (like Yamagata) and explicitly requires a surface microroughness of less than 10 Å (1.0 nm) for successful bonding.
    • Motivation to Combine: A POSITA implementing the ammonia plasma activation process from Yamagata would have looked to a reference like Bower, which details a similar process, to determine optimal process parameters. Bower’s express teaching that maintaining a low surface roughness (<1.0 nm) is required for successful low-temperature nitrogen bonding would have motivated a POSITA to apply this constraint to the process of Harendt and Yamagata.
    • Expectation of Success: A POSITA would expect that controlling the surface roughness of the Harendt/Yamagata bonding surface as taught by Bower would predictably result in a successful, strong bond, as this was a known requirement for the direct bonding process disclosed.

4. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 77, 79, 80-82, 84, 93-95, 99-101, 104-106, 110-114, 192, and 197 of the ’505 patent as unpatentable under 35 U.S.C. §103.