PTAB

IPR2019-00022

Samsung Electronics Co Ltd v. Invensas Bonding Technologies Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Bonding at Low or Room Temperature
  • Brief Description: The ’505 patent discloses methods for low-temperature semiconductor wafer bonding to achieve high bond strength. The process involves planarizing a bonding layer, slightly etching the layer to activate the surface, terminating the surface with a desired chemical species, and then bonding it to another surface.

3. Grounds for Unpatentability

Ground 1: Obviousness over Harendt and Yamagata - Claims 77, 79-82, 93-95, 104, 110-114, 192, and 197 are obvious over Harendt in view of Yamagata.

  • Prior Art Relied Upon: Harendt (a 1998 Electrochemical Society publication) and Yamagata (Japan Patent Appl. Laid-Open Pub. No. H7-249749).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Harendt disclosed the core bonded structure of independent claim 77, including a processed semiconductor device wafer (a "preprocessed CMOS substrate") with a planarized insulating oxide layer. However, Harendt did not explicitly teach etching and terminating the bonding surface. Yamagata allegedly supplied these missing elements by teaching a method to improve bonding strength through plasma activation. This process both etches the surface and terminates it with reactive species (e.g., from an ammonia or oxygen plasma) to create stronger bonds at low temperatures.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to improve the bonding process in Harendt's specific application (a vertically integrated image sensor). Petitioner asserted a POSITA would look to a reference like Yamagata to learn how to create a stronger, more reliable bond with fewer voids, especially for temperature-sensitive structures containing CMOS circuitry, which benefits from Yamagata's low-temperature annealing process.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying known techniques (plasma activation) to a known system (direct wafer bonding of oxide surfaces) to achieve the predictable result of a stronger bond.

Ground 2: Obviousness over Harendt, Yamagata, and Tong - Claims 84, 105, and 106 are obvious over Harendt in view of Yamagata and Tong.

  • Prior Art Relied Upon: Harendt, Yamagata, and Tong (a 1994 Materials Chemistry and Physics journal article).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the Harendt and Yamagata combination by adding Tong to address limitations in dependent claims. Petitioner contended Tong taught the benefits of thinning one wafer of a bonded pair to create stronger bonds by allowing surface molecules to get closer (addressing claim 84's "thinned silicon substrate" limitation). Tong also disclosed bonding wafers with a "native oxide" surface, a well-understood method at the time (addressing claim 105's "native oxide layer" limitation).
    • Motivation to Combine: A POSITA, seeking to further strengthen the bonded structure disclosed in Harendt and improved by Yamagata, would have been motivated to incorporate Tong's teaching to thin the CMOS substrate. Thinning was a known technique for improving bond strength. Additionally, using a native oxide layer as a bonding surface was a common, predictable, and well-understood alternative, making its application to the Harendt/Yamagata process an obvious design choice.
    • Expectation of Success: The combination was argued to be predictable, as it involved incorporating established techniques (wafer thinning, use of native oxide) into a direct wafer bonding process to achieve the known benefits of increased bond strength and process simplification.

Ground 3: Obviousness over Harendt, Yamagata, and Bower - Claims 99-101 are obvious over Harendt in view of Yamagata and Bower.

  • Prior Art Relied Upon: Harendt, Yamagata, and Bower (Patent 5,503,704).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground adds Bower to the Harendt/Yamagata combination to teach the surface roughness limitations of claims 99-101. While Yamagata taught an ammonia plasma activation process that etches the surface, it did not specify a required surface roughness. Bower, which also discloses a low-temperature direct bonding process using ammonia plasma activation, explicitly taught that successful bonding requires a surface microroughness of less than 10 Å (1.0 nm). This range inherently meets the claimed ranges of "between about 0.1 and 3.0 nm" (claim 99) and "between about 0.5 and 1.0 nm" (claim 100).
    • Motivation to Combine: A POSITA implementing the ammonia plasma process from Yamagata on Harendt's structure would have been motivated to consult a reference like Bower, which describes an identical nitrogen-based bonding process. Bower provided a critical, known process parameter—surface microroughness—necessary to ensure a successful, strong bond. It would have been obvious to apply Bower's explicit roughness requirement to the similar process in Yamagata to ensure its efficacy.
    • Expectation of Success: A POSITA would expect that controlling the surface roughness of the plasma etching process to meet Bower's specification would predictably result in a successful low-temperature bond, as both Yamagata and Bower used the same fundamental bonding chemistry.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 77, 79-82, 84, 93-95, 99-101, 104-106, 110-114, 192, and 197 of the ’505 patent as unpatentable under 35 U.S.C. §103.