Qualcomm Inc. v. Apple Inc.

1. Case Identification

• Patent #: 7,383,453
• Filed: November 11, 2018
• Petitioner(s): Qualcomm Inc. and Qualcomm Technologies, Inc.
• Patent Owner(s): Apple Inc.
• Challenged Claims: 1-4 and 8-11

2. Patent Overview

• Title: Conserving Power by Reducing Voltage Supplied to an Instruction-Processing Portion of a Processor
• Brief Description: The ’453 patent relates to methods and systems for reducing static power leakage in a processor, a problem distinct from managing dynamic power consumption. The invention describes an instruction-processing system partitioned into a "core" containing instruction-processing circuitry and a separate "area." The system implements multiple, distinct power-saving modes that independently control the clock signals and voltage levels supplied to the core to achieve a tiered approach to power savings.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 and 8-9 are anticipated by Ober.

• Prior Art Relied Upon: Ober (Patent 6,665,802).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ober, which was not considered during the original prosecution or a subsequent ex parte reexamination, discloses every element of independent claims 1 and 8. Ober describes a System-on-Chip (SoC) architecture for a microcontroller featuring a power management state machine to control multiple power modes. Petitioner contended that Ober’s CPU core 22, described as a 32-bit RISC-like core, directly maps to the claimed “core with instruction-processing circuitry.” The various subsystems external to the CPU core, such as the interrupt control unit (ICU), memory, and peripherals, collectively constitute the claimed “area coupled to the core.” Ober’s disclosed power modes were argued to correspond directly to those claimed:
    • The “RUN” mode, where the system is "fully operational," represents the claimed “normal operation mode.”
    • The “IDLE” mode, where core CPU clocks are stopped but all subsystems remain powered, represents the “first power-saving mode.”
    • The “SLEEP” mode, where the core clock is stopped and the CPU is unpowered, represents the “second power-saving mode,” with a core voltage less than the first value.
  • Key Aspects: Petitioner emphasized that Ober explicitly discloses the distinct exit mechanisms required by the claims. The “IDLE” mode can be exited upon receipt of an interrupt signal. The “SLEEP” mode can be exited by non-interrupt signals, such as a “watchdog reset or external signal.” This direct mapping allegedly satisfies all limitations of the independent claims.

Ground 2: Claims 1-2 and 8-9 are anticipated by Fung '011.

• Prior Art Relied Upon: Fung '011 (Patent 7,134,011).

• Core Argument for this Ground:

  • Prior Art Mapping: As an alternative to Ober, Petitioner asserted that Fung '011, also new art, teaches a complete instruction-processing system with multiple power-saving modes that anticipates claims 1 and 8. Fung '011’s CPU 320 was identified as the claimed “core,” and its “CPU core logic” 330, which includes a power management unit (PMU), was identified as the claimed “area.” Petitioner mapped Fung '011’s numerous operating modes to the claims, highlighting that the patent explicitly allows for any combination of its disclosed modes.
    • “Mode 1” (maximum clock and voltage) corresponds to the “normal operation mode.”
    • “Mode 3’” (clock off, voltage sufficient to maintain state) corresponds to the “first power-saving mode.”
    • “Mode 3’’” (clock off, voltage just sufficient to maintain state) corresponds to the “second power-saving mode,” where the voltage is less than the normal operating voltage.
  • Key Aspects: Fung '011 teaches that its power modes can be exited via various signals. An incorporated reference, Fung '025, shows exit from a similar mode via a non-maskable interrupt (an interrupt signal). Fung '011 itself describes exiting suspend mode via a resume signal from a real-time clock (RTC), which is a non-interrupt signal. This flexibility in exit triggers was argued to satisfy the limitations for both power-saving modes.

• Additional Grounds: Petitioner asserted that dependent claims 3-4 and 10-11, which add limitations for a cache and cache tags within the "area," are obvious over either Ober or Fung '011 in view of DeSchepper (Patent 5,721,935). DeSchepper was cited for its disclosure of a conventional cache system in a power-managed computer. Petitioner argued that a POSITA would be motivated to add a conventional cache from DeSchepper to the modular systems of Ober or Fung '011 to achieve the well-known and predictable benefit of improved processor performance by reducing memory latency. This combination was characterized as a simple application of a known technique to a similar system to yield a predictable result.

4. Key Claim Construction Positions

• "core" and "area": Petitioner argued that "core" should be given its plain and ordinary meaning, and "area" should be construed as "a portion of the processor excluding a core." This construction is critical as it allows the partitioned architectures in Ober (CPU core vs. other subsystems) and Fung '011 (CPU vs. core logic) to meet the claim limitations. Petitioner noted that these constructions are consistent with positions taken by the Patent Owner and were adopted by the district court in a related litigation (Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-1375 (S.D. Cal.)).
• "sufficient to maintain the state information...": Petitioner contended this phrase should be construed as "at least a value that maintains the state information of the instruction-processing circuitry." This interpretation is crucial for the mapping of the "first power-saving mode," where prior art like Ober maintains the normal operating voltage (which is "at least" the minimum required) while the clock is stopped.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-4 and 8-11 of the ’453 patent as unpatentable under 35 U.S.C. § 102 and § 103.