PTAB

IPR2019-00296

Qualcomm Inc v. Apple Inc

Key Events

Petition

petition

Title: Conserving Power by Reducing Voltage Supplied to an Instruction-Processing Portion of a Processor
Brief Description: The ’453 patent discloses an instruction-processing system with multiple power-saving modes to reduce static power leakage. The system comprises a separate "core" and "area," allowing for independent control of voltage levels and clock frequencies to each portion to achieve different levels of power savings.

Prior Art Relied Upon: Ober (Patent 6,665,802).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Ober, which discloses a power management architecture for a System-on-Chip (SoC), teaches every element of independent claims 1 and 8. Ober’s CPU core 22 was mapped to the claimed "core," and its external subsystems (interrupt controller, peripherals) were mapped to the "area." Petitioner asserted that Ober’s three distinct power modes directly correspond to those required by the claims:
  - Ober’s "RUN" mode, where the system is fully operational, allegedly meets the limitations of the claimed "normal operation mode."
  - Ober's "IDLE" mode, where the CPU clock is stopped but subsystems remain powered, allegedly meets the "first power-saving mode," which is exited upon an interrupt.
  - Ober’s "SLEEP" mode, where the CPU clock is stopped and the CPU is unpowered, allegedly meets the "second power-saving mode," which is exited upon a non-interrupt signal like a watchdog reset.
- Key Aspects: For dependent claims 2 and 9, Petitioner argued that Ober explicitly teaches exiting the "IDLE" mode via a "Reset," a signal that is not an interrupt, thereby anticipating those claims.

Prior Art Relied Upon: Ober (Patent 6,665,802), DeSchepper (Patent 5,721,935).
Core Argument for this Ground:
- Prior Art Mapping: This ground addressed dependent claims requiring the "area" to comprise a cache (claims 3 and 10) and cache tags (claims 4 and 11). Petitioner asserted that Ober discloses the base system with multiple power modes, and DeSchepper discloses a conventional CPU architecture that includes a cache memory and associated tag RAMs coupled to the CPU. A POSITA would have found it obvious to incorporate the conventional cache system from DeSchepper into the "area" of Ober's modular SoC architecture.
- Motivation to Combine: Petitioner argued a POSITA would combine these references to solve the common problem of reducing power consumption in portable devices while improving performance. Adding a cache, a well-known technique for increasing processor efficiency, to Ober's power-managed SoC was presented as a predictable design choice.
- Expectation of Success: The combination was argued to be straightforward and predictable, as Ober describes a "modular" architecture suitable for adding subsystems, and DeSchepper describes its cache as "conventional." A POSITA would expect the combination to yield the known benefits of caching without undue experimentation.

Prior Art Relied Upon: Fung ’011 (Patent 7,134,011).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Fung ’011, which teaches a modular server system with dynamic power management, discloses all limitations of the independent claims. The "CPU 320" in Fung ’011 was identified as the claimed "core," and the "CPU core logic" as the "area." Petitioner mapped the multiple power modes in Fung ’011 to the claimed modes:
  - "Mode 1" in Fung ’011, with maximum voltage and clock frequency, allegedly corresponds to the "normal operation mode."
  - "Mode 3'" in Fung ’011, where the core clock is inactive but voltage is sufficient to maintain CPU state, allegedly corresponds to the "first power-saving mode," which can be exited by an interrupt.
  - "Mode 3''" in Fung ’011, where the clock is stopped and core voltage is reduced to a level just sufficient to maintain state, allegedly corresponds to the "second power-saving mode," which can be exited by a non-interrupt signal from a real-time clock (RTC).

"core" and "area": Petitioner argued for adopting the constructions from a related district court litigation. "Core" was proposed as having its plain and ordinary meaning, and "area" was proposed as "a portion of the processor excluding a core." These constructions do not require any specific components to be included in either region.
"sufficient to maintain the state information...": Petitioner argued for construing this phrase as "at least a value that maintains the state information of the instruction-processing circuitry." This interpretation establishes a minimum voltage threshold but does not preclude higher voltages.

Petitioner requests institution of an inter partes review and cancellation of claims 1-4 and 8-11 of the ’453 patent as unpatentable.