PTAB

IPR2019-00297

Qualcomm Inc v. Apple Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Conserving Power by Reducing Voltage Supplied to an Instruction-Processing Portion of a Processor
  • Brief Description: The ’940 patent discloses a processor architecture designed to reduce power consumption. The system is divided into two distinct regions: a "core power area" containing instruction-processing components and a "non-core power area" with other components. The key feature involves halting operations in the core power area while the non-core power area remains operable.

3. Grounds for Unpatentability

Ground 1: Claims 9-11 and 15 are obvious over Ober in view of Dai.

  • Prior Art Relied Upon: Ober (Patent 6,665,802) and Dai (Patent 6,792,551).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that the combination of Ober and Dai teaches every element of the challenged claims. Ober was asserted to teach a base System-on-Chip (SoC) architecture with a central processing unit (CPU) core and various peripheral subsystems. Crucially, Ober disclosed power-saving modes, such as an "IDLE" mode, where the clock to the CPU core is stopped ("halted") while other non-core components (like an interrupt control unit and real-time clock) remain powered and operational. This was argued to satisfy the main functional limitation of the challenged claims. However, Ober allegedly did not explicitly detail the specific arrangement of all components as claimed.

      To supply the missing elements, Petitioner asserted that Dai teaches the specific partitioning of a processor into separate "core" and "non-core" power domains, each receiving a distinct voltage supply. Dai explicitly placed components like an L2 cache and a snoop controller in its non-core power area, while placing an L1 cache, execution units (ALU), and registers in its core power area. Petitioner contended that a person of ordinary skill in the art (POSITA) would have found it obvious to implement Ober's power-saving scheme using the specific and more advanced component partitioning taught by Dai. For example, a POSITA would integrate Dai's non-core components (L2 cache, snoop controller) and core components (L1 cache, ALU, pipelines) into Ober's corresponding architectural areas to achieve the claimed processor configuration.

    • Motivation to Combine: Petitioner asserted a strong motivation to combine the references, as both Ober and Dai were directed to solving the same fundamental problem: reducing power consumption in battery-powered portable devices. A POSITA seeking to design a power-efficient processor would have naturally looked to both references. Petitioner argued that Ober provides a "modular" power management architecture that is amenable to incorporating additional subsystems. A POSITA would have been motivated to incorporate the advanced cache and power domain structures from Dai into Ober’s system to improve overall processor performance and efficiency, which were well-known benefits of such components.

    • Expectation of Success: The combination was argued to be straightforward and would have yielded predictable results. Adding known components like caches and a snoop controller (from Dai) to a modular processor architecture (from Ober) was a common design practice. A POSITA would have reasonably expected the combined system to function as intended, achieving both the power-saving benefits of Ober's clock-halting scheme and the performance benefits of Dai's advanced cache architecture without any undue experimentation.

4. Key Claim Construction Positions

  • "power area": Petitioner requested that the Board construe this term according to its plain and ordinary meaning. This position was noted as being consistent with a claim construction order from a related district court litigation involving the ’940 patent (Qualcomm Inc. v. Apple Inc., No. 3:17-cv-1375 (S.D. Cal.)).

5. Key Technical Contentions

  • Petitioner argued that the inventive concept of the ’940 patent was tenuous because the patent's own specification acknowledged that its key limitation—halting clock signals to a portion of a processor while another portion remains operable—was already "known in the art." The petition highlighted that the claims were only allowed during prosecution after the applicant added this "halting" limitation to overcome an obviousness rejection based on the arrangement of processor components. Petitioner contended this prosecution history demonstrates that the allegedly novel feature was, by the patentee's own admission, a conventional technique.

6. Relief Requested

  • Petitioner requested that the Board institute an inter partes review and cancel claims 9-11 and 15 of the ’940 patent as unpatentable under 35 U.S.C. §103.