PTAB

IPR2019-00321

Qualcomm Inc. v. Apple Inc.

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1. Case Identification

  • Patent #: 8,271,812
  • Filed: November 12, 2018
  • Petitioner(s): QUALCOMM INC. AND QUALCOMM TECHNOLOGIES, INC.
  • Patent Owner(s): APPLE INC.
  • Challenged Claims: 8 and 9

2. Patent Overview

  • Title: Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events
  • Brief Description: The ’812 patent discloses a power management unit (PMU) for an integrated circuit, such as a system-on-chip (SoC). The PMU is designed to automatically transition, in hardware, the performance states of various "performance domains" within the SoC in response to a processor entering or exiting sleep and wake states, aiming to reduce power consumption and transition latency.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 8 and 9 under 35 U.S.C. §102

  • Prior Art Relied Upon: Mandelblat (Application # 2007/0043965).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Mandelblat discloses all elements of claims 8 and 9. Mandelblat teaches an apparatus (a microprocessor) with a plurality of components (e.g., Core 1 and a Dynamically Sizeable Memory) that reside in separate performance domains, as their performance states can be controlled independently. It discloses a Power Management Logic (PML) that functions as the claimed power management unit, configured to establish performance states for each domain (C-states for the core, cache size for the memory). The PML is configured to transition the memory's performance domain (by changing cache size) responsive to a processor core transitioning from a sleep state (C4) to a wakeup state (C0). Petitioner asserted that the wakeup state is different from a prior performance state, as the associated memory cache size has changed, fulfilling the final limitation of claim 8. For claim 9, Petitioner argued the PML transitions each performance domain (the core and the memory) into a respective power state responsive to the processor state change.

Ground 2: Obviousness of Claims 8 and 9 over Mandelblat in view of Kurts

  • Prior Art Relied Upon: Mandelblat (Application # 2007/0043965) and Kurts (Patent 7,363,523).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Mandelblat provides the foundational system with multiple components in distinct performance domains and a PMU to manage them. Kurts, which addresses the same problem of reducing latency in power state transitions, discloses waking a processor into a Low Frequency Mode (LFM) that is distinct from the High Frequency Mode (HFM) it operated in before sleeping. The combination renders it obvious to apply Kurts's method of transitioning to a different wakeup state (LFM) to Mandelblat's system, thereby teaching a wakeup state that is different from the prior performance state, as required by claim 8. The combination's PMU would transition at least one of Mandelblat's performance domains in response to this processor state change.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Mandelblat and Kurts because they are analogous arts that address the same problem of power management and latency reduction in computing systems. Both disclose using ACPI-based power states and were assigned to the same entity (Intel). A POSITA would combine Kurts's efficient wake-state management with Mandelblat's granular control over different performance domains (like cache and cores) to achieve predictable benefits in power efficiency and performance.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because combining these known power management techniques within the common ACPI framework would predictably yield improved power savings and reduced latency, the stated goals of both references.

Ground 3: Obviousness of Claims 8 and 9 over Kurts in view of Kang

  • Prior Art Relied Upon: Kurts (Patent 7,363,523) and Kang (Patent 7,369,815).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Kurts provides the core teachings of a PMU that transitions a processor between sleep and wake states, including waking into a different performance state (LFM). Kang, which was considered during prosecution but not in this combination, explicitly discloses partitioning a system into multiple, independently controllable "collapsible power domains." The combination of Kurts's state transition logic with Kang's explicit architecture of independent power domains would have rendered claim 8 obvious. The PMU from Kurts, when applied to a system with Kang's explicit domains, would be configured to transition those domains responsive to processor sleep/wake events. For claim 9, Kang explicitly discloses a power controller that transitions its various collapsible power domains responsive to the processor waking up.
    • Motivation to Combine: A POSITA would combine Kurts and Kang as they are in the same field of processor power management and address the shared goal of power reduction in portable devices. The examiner had previously found that Kang taught most elements of the claims. Petitioner argued a POSITA would have been motivated to apply Kurts's more detailed state transition methods to Kang's explicit power domain architecture to create a more robust and granular power management system.
    • Expectation of Success: A POSITA would expect success in combining these compatible technologies to achieve greater power savings, as it involves applying a specific control method (from Kurts) to a known system architecture (from Kang).

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 3) against claim 9 based on Mandelblat in view of Lint (Patent 7,426,648), relying on a similar motivation to combine analogous art to achieve more granular power control.

4. Key Claim Construction Positions

  • "performance domain": Petitioner noted that the District Court in related litigation adopted the Patent Owner's proposed construction: "one or more components that may be controlled as a unit or independently for performance configuration purposes." Petitioner argued that the Board should adopt at least this broad construction for the IPR. This construction is important as it allows a single component to be a "performance domain" and supports Petitioner's mapping of the prior art.
  • "power management unit": Petitioner agreed with the District Court's construction of "hardware or the combination of hardware and software." This counters any implication that the PMU must be solely hardware, which is consistent with the software and microcode-based control logic disclosed in the prior art.
  • "a prior performance state at which the processor was operating prior to entering the sleep state": Petitioner argued for the plain and ordinary meaning, which refers to a performance state at which the processor was operating "some time before" entering sleep. This is broader than the Patent Owner's proposed "last operating" state. This broader construction is critical to the anticipation argument, as it allows the "prior performance state" to be a state before the system's memory cache (a separate performance domain) began to shrink in preparation for the processor's sleep state.

5. Relief Requested

  • Petitioner requested that the Board institute an inter partes review and cancel claims 8 and 9 of the ’812 patent as unpatentable.