Qualcomm Inc v. Apple Inc

1. Case Identification

• Case #: IPR2019-00321
• Patent #: Patent 8,271,812
• Filed: November 12, 2018
• Petitioner(s): Qualcomm Inc. and Qualcomm Technologies, Inc.
• Patent Owner(s): Apple Inc.
• Challenged Claims: 8-9

2. Patent Overview

• Title: Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events
• Brief Description: The ’812 patent discloses an integrated circuit, such as a System-on-Chip (SoC), with multiple "performance domains" containing components like processors and memory. The invention centers on a hardware-based power management unit (PMU) that automatically transitions the performance states of these domains (e.g., adjusting voltage, frequency, or cache size) in response to a processor entering or exiting a sleep state to conserve power.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 8-9 are anticipated by [Mandelblat](https://ai-lab.exparte.com/case/ptab/IPR2019-00321/doc/1003) under 35 U.S.C. § 102.

• Prior Art Relied Upon: Mandelblat (Application # 2007/0043965).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mandelblat discloses all elements of the challenged claims. Mandelblat’s processor (901) was described as an apparatus with a plurality of components (e.g., Core 1, Dynamically Sizeable Memory) residing in separate performance domains. Its Power Management Logic (PML 906) allegedly functions as the claimed power management unit, establishing performance states for each domain (e.g., C-states for the core, cache size for the memory). Petitioner asserted that the PML is configured to transition the memory performance domain by expanding cache size responsive to the core transitioning from a sleep state (C4) to a wakeup state (C0). This wakeup state is different from the prior performance state because the associated cache size has changed, allegedly fulfilling the final limitation of independent claim 8. Dependent claim 9 was also asserted to be disclosed, as the PML transitions each domain (core and memory) responsive to the processor changing state.

Ground 2: Obviousness over Core Power Management References - Claims 8-9 are obvious over Mandelblat in view of [Kurts](https://ai-lab.exparte.com/case/ptab/IPR2019-00321/doc/1004).

• Prior Art Relied Upon: Mandelblat (Application # 2007/0043965) and Kurts (Patent 7,363,523).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mandelblat provides the primary system with a PMU managing distinct performance domains. Kurts was cited for its teaching of reducing latency by transitioning a processor from a deep sleep state to an intermediate, active wakeup state that operates in a Low Frequency Mode (LFM), which is distinct from the High Frequency Mode (HFM) it operated in before sleep. Petitioner contended that combining Kurts’s efficient transition to a distinct wakeup state (LFM) with Mandelblat’s system of managing performance domains would have rendered the claims obvious.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine these analogous references to achieve greater power savings and reduced latency, which were well-known goals. Both references address power management in microprocessors using ACPI-based states. Petitioner argued it would have been a simple design choice to implement Kurts’s more efficient wakeup method within Mandelblat’s power management architecture.
  • Expectation of Success: The combination involved applying known techniques in a predictable way, leading to the expected and beneficial results of improved power efficiency and performance.

Ground 3: Obviousness over Granular Power Control References - Claims 8-9 are obvious over Kurts in view of [Kang](https://ai-lab.exparte.com/case/ptab/IPR2019-00321/doc/1006).

• Prior Art Relied Upon: Kurts (Patent 7,363,523) and Kang (Patent 7,369,815).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Kurts provides a processor with various power states (C-states) and a PMU to manage transitions but does not explicitly detail partitioning components into distinct performance domains. Kang was cited for its disclosure of a processor partitioned into multiple "collapsible" power domains that can be independently powered on or off by a central power control unit. Petitioner contended it would have been obvious to apply Kang’s explicit teaching of independent power domains to the components within Kurts’s processor, thereby arriving at the claimed invention. The examiner had previously considered the Kang application alone but not its combination with Kurts.
  • Motivation to Combine: A POSITA would combine Kurts’s efficient state transition logic with Kang’s granular, independent power domain management to achieve greater overall power savings. Both references are in the same technical field, address power conservation, and were filed closely in time.
  • Expectation of Success: Combining the known concepts of domain-based power gating from Kang with C-state management from Kurts would have been a straightforward integration with a high expectation of achieving the predictable result of enhanced power conservation.
• Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 9 based on Mandelblat in view of Lint (Patent 7,426,648), arguing Lint’s disclosure of a power module adjusting performance resources for multiple logical processors would have rendered claim 9’s “transition each” limitation obvious.

4. Key Claim Construction Positions

• The petition argued for constructions at least as broad as those adopted in a related district court case while contesting certain narrower interpretations.
• "performance domain": Petitioner accepted the court's construction of "one or more components that may be controlled as a unit or independently for performance configuration purposes," which supports the argument that components like a core and memory can have their states managed separately.
• "power management unit": Petitioner noted the court’s construction as "hardware or the combination of hardware and software," which is broader than the patent’s emphasis on a purely hardware-based PMU and therefore encompasses more prior art.
• "a prior performance state...": Petitioner contested the patent owner's narrow construction ("the last operating state"), arguing for the broader "a performance state...at which the processor was operating some time before entering the sleep state." This broader interpretation was asserted to be more consistent with the specification and more easily met by the prior art.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 8-9 of the ’812 patent as unpatentable.