Qualcomm Inc v. Apple Inc

1. Case Identification

• Patent #: 8,656,196
• Filed: November 12, 2018
• Petitioner(s): Qualcomm Inc. and Qualcomm Technologies, Inc.
• Patent Owner(s): Apple Inc.
• Challenged Claims: 1-3, 7, and 8

2. Patent Overview

• Title: Hardware Automatic Performance State Transitions In System On Processor Sleep And Wake Events
• Brief Description: The ’196 patent relates to managing power in an integrated circuit by transitioning the performance states of various "performance domains" and their components. A programmable power management unit (PMU) controls these transitions in response to a processor entering or exiting sleep and wake states.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, and 7-8 are anticipated by Mandelblat under 35 U.S.C. §102.

• Prior Art Relied Upon: Mandelblat (Application # 2007/0043965).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mandelblat discloses all elements of the challenged claims. Mandelblat teaches an apparatus with a processor comprising multiple components, such as a "Dynamically Sizeable Memory" and processor cores, which Petitioner asserted constitute separate "performance domains." Mandelblat’s Power Management Logic (PML) functions as the claimed "power management unit," using configuration data (e.g., microcode) stored in registers to define and establish different performance states for these domains. These states include varying cache memory sizes and core power states (C-states). The PML transitions these domains between states (e.g., full vs. minimum cache, awake vs. sleep) responsive to asynchronous events, such as a processor core entering a sleep state. This directly maps to the limitations of independent claims 1 and 7.
  • Key Aspects: The argument for dependent claims 2, 3, and 8 followed directly, as Mandelblat explicitly links the performance state transitions (e.g., cache resizing) to the processor core’s transitions into a sleep state (C4) and subsequent transitions to an awake state (C0).

Ground 2: Claims 1-3, and 7-8 are obvious over Mandelblat in view of Kurts under 35 U.S.C. §103.

• Prior Art Relied Upon: Mandelblat (Application # 2007/0043965) and Kurts (Patent 7,363,523).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Mandelblat provides the foundational system of a PMU managing performance domains (like dynamically sized memory) based on processor state. Kurts, addressing the same technical problem, teaches a more detailed method for managing power states to reduce latency when waking from sleep. Specifically, Kurts discloses waking a processor into an active but Low Frequency Mode (LFM), which is a distinct performance state from the High Frequency Mode (HFM) used before sleep. This LFM allows the processor to handle events quickly without the delay of ramping up to full frequency. The combination of Mandelblat’s architecture with Kurts’s nuanced state transition logic (e.g., having multiple distinct "awake" states) would teach every element of the challenged claims.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine the references to solve the common problem of optimizing power and performance. A POSITA would be motivated to integrate Kurts's efficient wake-up logic (LFM) into Mandelblat's system to gain the benefits of both dynamic resource management (Mandelblat) and reduced wake-up latency (Kurts). Petitioner noted that both references are assigned to Intel, address ACPI-based power management, and share a common co-inventor, further suggesting a motivation to combine their teachings.
  • Expectation of Success: The combination involved applying known power management techniques (state transitions, frequency scaling) within a conventional processor architecture. A POSITA would have had a high expectation of success in combining the systems to achieve the predictable result of improved power efficiency and system responsiveness.

Ground 3: Claims 1-3, and 7-8 are obvious over Kurts in view of Kang.

• Prior Art Relied Upon: Kurts (Patent 7,363,523) and Kang (Patent 7,369,815).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner contended that Kurts teaches a processor with a PMU that controls transitions between various power states (C-states), including multiple awake and sleep states. While Kurts teaches powering down portions of processor circuitry, it does not explicitly use the term "performance domains." Kang explicitly discloses partitioning a processor into distinct "power domains" that can be independently powered on or off ("collapsed") by a dedicated power control unit to conserve power. Combining Kurts's advanced state-transition management with Kang's explicit architecture of independently controllable power domains would result in the apparatus claimed in the ’196 patent.
  • Motivation to Combine: A POSITA seeking to improve the power efficiency of the system in Kurts would look to other known techniques for granular power control. Kang provides an explicit and well-understood method of partitioning a system into independent power domains. A POSITA would combine Kang's domain-based power collapse with Kurts's state-based control to achieve more comprehensive power savings, a routine design goal in processor architecture.
  • Expectation of Success: Both references describe compatible, well-known techniques for processor power management. Integrating Kang's domain partitioning with Kurts's state control logic would have been a straightforward design choice with a predictable outcome of enhanced power savings.

4. Key Claim Construction Positions

Petitioner proposed that the Board adopt claim constructions consistent with those from the related district court litigation (Qualcomm Inc. v. Apple Inc., Case No. 3:17-cv-1375).

• "performance domain": Construed as "one or more components that may be controlled as a unit or independently for performance configuration purposes." Petitioner argued this construction, advanced by the Patent Owner in litigation, allows components within a domain to be controlled independently.
• "power management unit": Construed as "hardware or the combination of hardware and software," not limited to a hardware-only implementation.
• "establish a ... performance state": Argued to mean "set the one or more performance characteristics to the appropriate values for the performance state," which does not require an actual transition to occur at the moment of establishment.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-3, 7, and 8 of the ’196 patent as unpatentable.