PTAB
IPR2019-00643
Kingston Technology Co Inc v. Memory Technologies LLC
Key Events
Petition
Table of Contents
petition Intelligence
1. Case Identification
- Case #: IPR2019-00643
- Patent #: RE45,486
- Filed: January 30, 2019
- Petitioner(s): Kingston Technology Company, Inc.
- Patent Owner(s): Memory Technologies, LLC
- Challenged Claims: 6, 8-11, 23, 25-27, and 30-31
2. Patent Overview
- Title: Memory Card, a Method for Addressing Memory Locations of a Memory Card, and a Device
- Brief Description: The ’486 patent discloses a memory card that supports multiple addressing methods to overcome memory capacity limits of existing standards. The card stores "addressing data" that indicates whether it supports a "basic" or an "expanded" addressing method, allowing it to access a larger number of memory locations than would otherwise be possible.
3. Grounds for Unpatentability
Ground 1: Anticipation over Toombs - Claims 6, 8-11, 25-27, and 30-31 are anticipated by Toombs.
- Prior Art Relied Upon: Toombs (Patent 6,279,114).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Toombs, which describes a MultiMediaCard (MMC) system, discloses every limitation of the challenged claims. Toombs's Card-Specific Data (CSD) register stores parameters used to calculate memory capacity, such as
C_SIZE. Crucially, Toombs discloses aREAD_BL_PARTIALbit in the CSD register that serves as the claimed "addressing data." When this bit is '0', the card operates in a block-oriented transfer mode (an "expanded" method enabling addressing of a full 512-byte block). When the bit is '1', the card permits partial block reads, allowing the host to address smaller data units, down to a single byte (a "basic" method). - Key Aspects: Petitioner contended that the state of the
READ_BL_PARTIALbit directly indicates one of two supported addressing methods, with the expanded method (full block reads) enabling access to a larger number of total memory locations (512 bytes) compared to the basic method (a single byte location). A similar disclosure regarding aWRITE_BL_PARTIALbit was also presented as anticipating the claims.
- Prior Art Mapping: Petitioner argued that Toombs, which describes a MultiMediaCard (MMC) system, discloses every limitation of the challenged claims. Toombs's Card-Specific Data (CSD) register stores parameters used to calculate memory capacity, such as
Ground 2: Obviousness over Toombs and Dent - Claims 6, 8-11, 23, 25-27, and 30-31 are obvious over Toombs in view of Dent.
- Prior Art Relied Upon: Toombs (Patent 6,279,114) and Dent (Patent 6,314,504).
- Core Argument for this Ground:
- Prior Art Mapping: To the extent Toombs was found not to teach a selectable addressing method, Petitioner argued Dent supplied the missing element. Dent discloses a processor architecture where mode bits in an index register are used to select between different addressing modes to increase efficiency and accessible memory. For example, a single bit selects between a "byte mode" using 31 address bits to access 2GB of memory and a "word mode" using 30 address bits to access 4GB of memory.
- Motivation to Combine: A POSITA would combine Toombs and Dent to solve the known problem of memory capacity limits in memory cards. Both references are analogous and address memory access in low-power devices. A POSITA would have been motivated to apply Dent’s established technique of using mode bits to switch addressing schemes to the memory card system of Toombs to achieve greater addressing capability in a predictable manner.
- Expectation of Success: Combining Dent's use of mode bits with Toombs's memory card architecture was a straightforward application of known design principles to achieve the predictable result of expanded memory addressing.
Ground 3: Obviousness over Toombs and PCMCIA - Claims 6, 8-11, 23, 25-27, and 30-31 are obvious over Toombs in view of the PCMCIA Standard.
Prior Art Relied Upon: Toombs (Patent 6,279,114) and the PCMCIA Standard (PC Card Standard, Volume 2 Electrical Specification, 1999).
Core Argument for this Ground:
- Prior Art Mapping: The PCMCIA standard, a leading mass storage standard, discloses overcoming addressing limits by using an expanded addressing method. Specifically, a data tuple stored in the card’s Card Information Structure (CIS) indicates whether the card supports an expanded mode that uses six additional address bits to increase addressable memory from 64MB (basic method) to 4GB (expanded method). This tuple constitutes the claimed "addressing data."
- Motivation to Combine: A POSITA seeking to expand the addressing capability of the Toombs card would have looked to other prominent standards like PCMCIA that had already solved this exact problem. It would have been obvious to store information indicating the supported addressing mode in a register on the Toombs card, analogous to how the PCMCIA standard stores a tuple in the CIS, to inform the host system which addressing method to use.
- Expectation of Success: Implementing a known solution from one memory card standard (PCMCIA) into another (the MMC card of Toombs) would have yielded the predictable result of enabling an expanded addressing mode.
Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) against claims 6, 8-11, 23, 25-27, and 30-31 based on Toombs in view of the ATA-6 Standard (Revision 3a). This ground relied on a similar theory that the ATA-6 standard taught using a stored bit to indicate support for an expanded 48-bit addressing mode over a basic 28-bit mode, and a POSITA would have been motivated to apply this known solution to Toombs.
4. Key Claim Construction Positions
- "addressing data": Petitioner proposed this term means "data indicative of an addressing method." This construction was central to its argument that a single bit or tuple in the prior art, which indicates which of two or more addressing schemes is supported, meets this limitation.
- "an addressing method": Petitioner proposed this term means "a technique of accessing data by way of its location." This broad construction allowed Petitioner to argue that different schemes like byte-addressing versus block-addressing, or using a different number of address bits, constituted distinct "addressing methods."
5. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 6, 8-11, 23, 25-27, and 30-31 of the ’486 patent as unpatentable.
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