PTAB

IPR2019-01039

Renesas Electronics Corp v. Broadcom Corp

Key Events

Petition

petition

Title: System for Clock Signal Distribution
Brief Description: The ’583 patent discloses a hybrid hardware-software system for power management in electronic devices using clock gating. The system employs a processor running software to flexibly activate or deactivate clock gates, allowing it to override or supplement a dedicated hardware control logic block that also manages the flow of clock signals to various components.

Prior Art Relied Upon: Kiuchi (Japanese Application # H08-225034) and Van Hook (Patent 6,593,929).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Kiuchi taught the core limitations of claim 17, disclosing a processor that writes to memory-mapped registers to turn clock gates ON or OFF, thereby controlling clock signals to various function units. While Kiuchi’s registers were readable, it did not explicitly teach the processor first reading a status from the register before writing to it.
- Motivation to Combine: Van Hook was asserted to supply the missing "read-before-write" functionality. Van Hook taught a main processor that first reads a status register to determine if a coprocessor is already halted (i.e., its clock is stopped) before conditionally writing to the register to change its state. A POSITA would combine Van Hook’s technique with Kiuchi’s system to improve performance and efficiency by avoiding unnecessary and slow serialized writes to control registers.
- Expectation of Success: A POSITA would have a high expectation of success, as both references described conventional systems using standard memory-mapped registers, making the proposed modification straightforward and predictable.

Prior Art Relied Upon: Ninomiya (Patent 5,764,968) and Van Hook (Patent 6,593,929).
Core Argument for this Ground:
- Prior Art Mapping: This ground presented a similar argument to Ground 1, but used Ninomiya as the primary reference. Petitioner asserted that Ninomiya disclosed a system with a CPU (an Intel Pentium processor) running software (BIOS) that writes to readable and writable control registers to selectively turn clock signals ON and OFF for various PCI devices and memory banks.
- Motivation to Combine: As in Ground 1, Petitioner argued a POSITA would be motivated to incorporate Van Hook’s "read-before-write" method into Ninomiya’s system for the same reason: to improve performance by reducing unnecessary register writes, which were known to be slow operations. The motivation was particularly strong as Ninomiya’s use of an Intel processor would be subject to the performance penalties of serialized instructions.
- Expectation of Success: The combination was argued to be predictable, as it involved applying a known optimization technique (from Van Hook) to a standard processor-and-register architecture (from Ninomiya).

Prior Art Relied Upon: Alben (Patent 6,938,176).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Alben taught every element of claims 25 and 26. Alben’s “control unit 12” was mapped to the claimed “hardware control logic block,” as it automatically controlled clock gates based on subsystem status. Alben’s “CPU 4” was mapped to the claimed “at least one processor,” and its “host slave unit 15” or system software was mapped to the “clock tree driver” that controls register 12A. Critically, Alben’s CPU 4, running system software, could intervene and write to the registers to change the hardware control unit’s mode (e.g., to FULLPOWER), thereby overwriting a status previously set by the hardware logic. This mapping, Petitioner noted, differed from the one unsuccessfully argued by the Examiner during the patent’s original prosecution.
Additional Grounds: Petitioner asserted additional obviousness challenges for claims 21 and 24 by adding Alben and Fallah (a 2002 book chapter on power management) to the Kiuchi/Van Hook and Ninomiya/Van Hook combinations. These grounds argued that Alben and Fallah provided explicit teachings on hybrid hardware/software power management systems, the design trade-offs involved, and the motivation for using software to override hardware decisions for greater flexibility and to implement more complex power-saving algorithms.

"at least one processor" (claim 25): Petitioner argued this term must be construed as a "processor adapted to execute code and separate from both the clock tree driver and the hardware control logic block."
- Rationale: This construction was supported by the claim language, which recited the processor, clock tree driver, and hardware control logic block as distinct elements. More importantly, Petitioner contended that during prosecution, the applicant overcame a rejection over Alben by arguing that Alben’s components did not separately meet these claimed elements. Therefore, prosecution history estoppel required that the elements be construed as structurally separate components.

Petitioner requests institution of IPR and cancellation of claims 17-18 and 20-26 as unpatentable.