PTAB

IPR2019-01040

Renesas Electronics Corp v. Broadcom Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Configurable Hardware Accelerators for Video Decoding
  • Brief Description: The ’844 patent discloses a digital media decoding system employing a core processor that controls multiple hardware accelerators. The accelerators are designed to be configurable, allowing the system to perform decoding functions that support a plurality of different video decoding formats and standards.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claims 1, 9-10 over Fandrianto

  • Prior Art Relied Upon: Fandrianto (Patent 5,982,459).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fandrianto taught a "universal" video communications processor system designed to solve the same problem as the ’844 patent—supporting multiple decoding standards. Fandrianto’s RISC processor 220 was asserted to be the claimed "processor" that controls a decoding pipeline. The system's video processor 280, H.221/BCH decoder, and Huffman decoder 268 were identified as hardware components that function as the claimed "hardware accelerator." Petitioner contended these accelerators were configurable by the RISC processor to support multiple standards (e.g., MPEG, H.261) via software loading or programming of internal registers and look-up tables.
    • Motivation to Combine (for §103 grounds): As a single-reference ground, the argument focused on inherent teachings and obvious modifications. Petitioner asserted that to achieve Fandrianto’s stated goal of a "universal" decoder, it would have been an obvious design choice for a person of ordinary skill in the art (POSITA) to ensure each hardware accelerator, including the Huffman decoder, was internally programmable. This was framed as a predictable application of known technology to achieve a predictable result.
    • Expectation of Success: Success was expected because modifying the components to be fully programmable was a straightforward implementation to achieve the reference's own objectives.

Ground 2: Obviousness of Claims 11-13 over Fandrianto in view of Fandrianto ’351 and Reader

  • Prior Art Relied Upon: Fandrianto (’459 patent), Fandrianto (Patent 5,379,351), and Reader (Patent 6,192,073).
  • Core Argument for this Ground: This combination was argued to disclose the specific types of hardware accelerators recited in dependent claim 11, building upon the base system taught by Fandrianto ’459.
    • Prior Art Mapping: Petitioner argued that Fandrianto ’459’s video processor 280, as a programmable signal processor, could be configured to perform the functions of an inverse quantizer and inverse transform accelerator. To the extent Fandrianto ’459 did not explicitly detail a "pixel filter" and "motion compensator," Petitioner pointed to Fandrianto ’351, which is expressly incorporated by reference into Fandrianto ’459 as describing the architecture of the video processor 280. Fandrianto ’351 explicitly discloses a vision processor with motion estimation and pixel interpolation capabilities. For the "programmable entropy decoder," Petitioner contended that Reader taught a programmable bitstream processor for entropy decoding, which a POSITA would have used to implement Fandrianto '459's Huffman decoder to enhance its flexibility.
    • Motivation to Combine: A POSITA would combine the teachings because Fandrianto ’459 expressly incorporates Fandrianto ’351. Further, a POSITA would combine Reader's processor-based entropy decoder into the Fandrianto ’459 system to better achieve the shared goal of a universal decoder capable of supporting new and custom standards, a known problem in the art.
    • Expectation of Success: Success was expected because the references describe analogous architectures for solving the same multi-standard video decoding problem, making integration routine.

Ground 3: Obviousness of Claim 14 over Fandrianto, Fandrianto ’351, Reader, and Harrand

  • Prior Art Relied Upon: Fandrianto (’459 patent), Fandrianto (’351 patent), Reader (’073 patent), and Harrand (Patent 5,995,513).
  • Core Argument for this Ground: This combination adds the final limitation from claim 14: a processor that reads registers of an accelerator to derive its operational status.
    • Prior Art Mapping: Petitioner argued that while Fandrianto ’459 taught a processor writing to registers to configure its accelerators, it did not explicitly disclose reading from those registers to determine operational status. Harrand was introduced to supply this teaching. Harrand discloses a multitask processing system where a processor (sequencer) reads a "status register" of an accelerator (operator) to determine if it is ready for a new command.
    • Motivation to Combine: A POSITA would combine Harrand's status-reading mechanism with the Fandrianto system as a well-known technique for managing a processing pipeline. Implementing readable status registers was presented as an obvious design choice to allow the main processor to efficiently supervise the various hardware accelerators, which is a predictable solution to a common problem in parallel processing systems.
    • Expectation of Success: The combination was asserted to be a predictable use of prior art elements according to their established functions, leading to an expectation of success.

4. Key Claim Construction Positions

  • "wherein the accelerator is configurable to perform the decoding function according to a plurality of decoding methods": Petitioner argued, consistent with the patent owner and prior constructions, that this term should be construed to mean "wherein the accelerator is internally programmable by the processor to perform its decoding function according to a plurality of decoding methods." This construction was central to the patent’s allowance and the invalidity arguments.
  • "programmable entropy decoder": Petitioner proposed this term be construed as a "processor that performs variable length decoding, arithmetic decoding, or variations on either of these." This construction was based on intrinsic evidence suggesting the term "programmable" was used to distinguish this specific accelerator from the other merely "configurable" hardware accelerators in claim 11.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1 and 9-14 of Patent 8,284,844 as unpatentable.