PTAB

IPR2019-01041

Renesas Electronics Corp v. Broadcom Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Access Unit for Accessing Data for a Module
  • Brief Description: The ’752 patent relates to a memory access unit (MAU) designed to improve the efficiency of data access for modules like video decoders. The MAU generates and queues requests for lists of data at potentially non-consecutive memory addresses and provides them to a memory controller over a dedicated link.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 5, 7, and 8 are obvious over Foster in view of Sih

  • Prior Art Relied Upon: Foster (Patent 6,240,492) and Sih (Application # 2003/0106053).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Foster discloses a memory interface for video decoding that is analogous to the claimed MAU and teaches nearly all limitations of claim 1. Specifically, Foster’s interface uses a dedicated memory port (the claimed "link") and a "large queue of multiple memory requests," which was the key feature added to the ’752 patent's claims to overcome prior art during original prosecution. Petitioner asserted that Sih, which addresses efficient video data processing, teaches the one element potentially not explicit in Foster: generating a single access request for a "list" of multiple, non-contiguous addresses. Sih’s VDMA controller fetches entire blocks of video data, including multiple non-contiguous rows, in response to a single command.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references as both seek to solve the well-known problem of improving memory access efficiency for motion compensation in video decoding. A POSITA would have recognized the benefit of incorporating Sih’s efficient method of requesting multiple non-contiguous addresses in a single command into Foster’s established queued architecture to further optimize system performance and reduce latency.
    • Expectation of Success: The combination involved applying known memory access and data fetching techniques to a similar system to achieve a predictable improvement in efficiency, presenting a straightforward task for a POSITA.

Ground 2: Claims 1, 2, 5, 7, and 8 are obvious over Foster in view of Rovati

  • Prior Art Relied Upon: Foster (Patent 6,240,492) and Rovati (Application # 2002/0031179).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative combination where Foster again provided the foundational MAU architecture, including the critical queue and dedicated link. Rovati was used as an alternative to Sih to teach the "list of addresses" limitation. Petitioner contended that Rovati’s "predictor fetch" block, used for motion estimation, gathers multiple blocks of pixel data and can issue a single request for multiple blocks, which inherently contain lists of multiple memory addresses.
    • Motivation to Combine: As with the first ground, a POSITA would combine Foster and Rovati because both address identical memory bandwidth challenges in video processing. It would have been obvious to apply Rovati’s efficient technique of using a single request to access all data needed for multiple blocks to Foster's system to improve its performance.
    • Expectation of Success: A POSITA would have had a high expectation of success in combining these compatible technologies to achieve the predictable advantage of increased data throughput.

Ground 3: Claims 1, 2, 5, 7, and 8 are obvious over Foster

  • Prior Art Relied Upon: Foster (Patent 6,240,492).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented this ground as an alternative contingent on adopting the Patent Owner's broader claim construction from a related proceeding, under which "access requests for lists of addresses" could be met by a series of requests for single addresses. Petitioner argued that Foster’s system, which generates "a series of eight requests with each address separated by a fixed value," directly meets this broader construction. Because Foster was argued to teach all other claim limitations, including the queue and dedicated link, it would render the claims obvious on its own.
    • Key Aspects: This argument was positioned as a fallback that obviates the need for a secondary reference if the Board adopts a claim construction less favorable to the Petitioner.

4. Key Claim Construction Positions

  • "access requests for lists of addresses in a memory": Petitioner argued this phrase requires that each individual access request must include a list of multiple memory addresses. This construction was central to their primary obviousness grounds (1 and 2), which relied on Sih or Rovati to teach this specific feature as an improvement to Foster’s base system.
  • "a link to a memory controller": Petitioner proposed this term should be construed as "a non-shared bus." This construction was based on the patent’s consistent differentiation between the claimed "link" (used exclusively by the MAU) and a "shared bus" (used by other clients). This interpretation makes Foster's "dedicated bus" a direct structural equivalent.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 2, 5, 7, and 8 of Patent 7,512,752 as unpatentable.