Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2019-01198
• Patent #: Patent 7,247,552
• Filed: June 21, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-2

2. Patent Overview

• Title: Integrated Circuit with Dummy Metal Fill Underneath a Bond Pad
• Brief Description: The ’552 patent discloses an integrated circuit (IC) structure designed to improve mechanical integrity during manufacturing. The invention involves placing dummy metal lines within interconnect layers in a defined "force region" underneath a bond pad to increase metal density and mitigate stress-related defects.

3. Grounds for Unpatentability

Ground I: Obviousness over Oda and Cwynar - Claims 1 and 2 are obvious over Oda in combination with Cwynar.

• Prior Art Relied Upon: Oda (Application # 2004/0150112) and Cwynar (Application # 2002/0162082).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Oda teaches the core concepts of the ’552 patent, including an IC with a stack of interconnect layers under a bond pad and the addition of "dummy patterns" in that region to absorb shock and prevent cracking during bonding. Petitioner contended Oda discloses all limitations of claim 1 except for the explicit use of metal "lines." Cwynar was introduced to supply this element, as it explicitly teaches adding dummy metal "lines" adjacent to active interconnects to achieve a uniform, predetermined metal density for improved planarity during polishing.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSA) would combine these references because they are in the same field (IC manufacturing) and address overlapping problems (planarity and structural integrity). A POSA would have been motivated to use Cwynar’s specific teaching of metal lines as one of Oda’s more generally described "patterns" to achieve the predictable benefits of improved shock resistance (from Oda) and uniform planarity (from Cwynar).
  • Expectation of Success: Petitioner asserted a POSA would have a reasonable expectation of success, as combining the references involved applying a known technique (using metal lines for dummy fill) to a known structure (Oda’s IC with dummy patterns) to achieve predictable results.

Ground II: Obviousness over Oda, Cwynar, and AAPA - Claim 2 is obvious over Oda in combination with Cwynar and Applicant Admitted Prior Art (AAPA).

• Prior Art Relied Upon: Oda (Application # 2004/0150112), Cwynar (Application # 2002/0162082), and AAPA from the ’552 patent specification.
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground I for the limitations of claim 1. Dependent claim 2 adds the limitation of "a conductive ball on the bond pad." Petitioner argued that the ’552 patent’s own specification admits that "[t]he use of conductive balls, such as solder balls, to make electrical connection to a bond pad is a known method." This admission constitutes AAPA.
  • Motivation to Combine: A POSA implementing the IC structure taught by the combination of Oda and Cwynar would need to connect it to external devices. Petitioner argued it would have been obvious to use the well-known and admittedly conventional method of a conductive ball for this purpose.
  • Expectation of Success: Adding a conventional conductive ball to the bond pad of the obvious structure from Ground I was presented as a simple and routine step with a high expectation of success.

Ground III: Obviousness over Oda and Owada - Claims 1 and 2 are obvious over Oda in combination with Owada.

• Prior Art Relied Upon: Oda (Application # 2004/0150112) and Owada (Patent 5,027,188).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Oda provides the foundational teaching of adding dummy patterns under a bond pad for shock resistance. Owada was cited to supply teachings of specific structural arrangements, including adding dummy metal lines adjacent to active functional lines directly below a bond pad. Owada further discloses functional metal lines (for signals) that are not electrically connected to the bond pad (which is used for power), satisfying another key limitation of claim 1. For claim 2, Owada explicitly discloses a solder bump (a conductive ball) on its electrode pad.
  • Motivation to Combine: A POSA would combine Oda and Owada as they both address planarity and structural integrity in ICs using dummy features. A POSA would be motivated to incorporate Owada’s specific implementation of co-located active and dummy lines into Oda's structure to achieve the combined, predictable benefits of improved planarity (from Owada) and shock resistance (from Oda).
  • Expectation of Success: Petitioner asserted that substituting Owada’s specific metal line patterns for Oda’s general patterns would be a predictable design choice for a POSA seeking to optimize both planarity and mechanical strength, with a high expectation of success.

4. Key Claim Construction Positions

• "force region": Petitioner argued this term, coined by the patentee, requires construction based on its explicit definition in the specification: "a region within the integrated circuit... in which forces are exerted on the interconnect structure when a die attach is performed." Petitioner contended the Patent Owner’s proposed construction in district court—"an area in which a defect may occur"—is improper because it ignores the patentee’s lexicography and would render other claim limitations, such as the region being "susceptible to defects," redundant.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) would be inappropriate. The petition asserted that the invalidity arguments were not previously presented to the USPTO, and that the complexity of parallel district court litigation involving numerous patents would limit its ability to fully present its invalidity case at trial. Petitioner also noted it was barred from pursuing Ground II in the district court action after being ordered to narrow its defenses, making the IPR the only forum for that challenge.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1 and 2 of the ’552 patent as unpatentable.