Intel Corp v. Tela Innovations Inc

1. Case Identification

• Case #: IPR2019-01228
• Patent #: 7,943,966
• Filed: June 19, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): Tela Innovations, Inc.
• Challenged Claims: 2, 31-33, and 35

2. Patent Overview

• Title: Semiconductor Device Layout with Restricted Layout Region
• Brief Description: The ’966 patent discloses a regular circuit layout style for semiconductor integrated circuits intended to improve manufacturing yields. The invention is characterized by a "dynamic array" architecture where features in layers above the substrate are restricted to linear-shaped structures oriented in parallel and positioned with a substantially equal centerline-to-centerline spacing.

3. Grounds for Unpatentability

Ground 1: Claims 2, 31-33, and 35 are obvious over Ichiryu.

• Prior Art Relied Upon: Ichiryu (Patent 7,503,026).

Core Argument for this Ground:

• Prior Art Mapping: Petitioner argued that Ichiryu teaches all limitations of the challenged claims. The ’966 patent’s claimed novelty, according to its prosecution history, hinges on a regular layout that includes at least one dummy gate. Petitioner contended that Ichiryu, which was not before the examiner, explicitly teaches this exact concept to solve the same problem of improving manufacturing precision and yield as device features shrink.
• Independent claim 2 recites an integrated circuit device with a gate electrode level region containing a plurality of linear conductive segments. Ichiryu was shown to disclose a regular layout for standard cells where both active gate electrodes (G) and dummy gate electrodes (DG) are arranged as parallel, linear structures extending in the same direction with a constant gate pitch. These structures in Ichiryu are conductive (e.g., polysilicon), have lengths greater than their widths, and are positioned side-by-side with a substantially equal centerline-to-centerline spacing, meeting all limitations of claim 2. Specifically, Ichiryu’s active gates (G) satisfy the limitation of segments forming gate electrodes for transistors of different types, while its dummy gates (DG) satisfy the key limitation of a segment that does not form a gate electrode of a transistor device.
• Dependent claims 31-33 and 35 add limitations related to multi-layer interconnects. Petitioner argued that Ichiryu also discloses a multi-layer interconnect architecture to be used with its regular gate layout. Ichiryu teaches that different wiring layers are used for wirings in the X and Y directions (i.e., orthogonal to each other). This directly maps to the claims’ requirements for a first interconnect level with structures parallel to the gate segments and a second interconnect level with structures perpendicular to them. Ichiryu further teaches that the interconnects are placed on a regular routing grid, and that the pitch of this grid (Lx) can be set to be equal to the gate pitch (Gx), thereby satisfying the claim 32 limitation that the interconnect spacing is an integer multiple (i.e., 1x) of the gate segment spacing.

4. Key Claim Construction Positions

• Petitioner argued that several terms required construction but that the challenged claims are obvious under either party's proposed constructions. The most critical disputed term was "linear conductive segment(s) / linear conductive structure(s)."

Petitioner's Proposed Construction:

• "having a consistent vertical cross-section shape and extending in a single direction over the substrate."

Rationale:

• Petitioner asserted this construction was taken directly from an explicit definition in the ’966 patent's specification, which states: "A linear-shaped layout feature in a given layer is characterized as having a consistent vertical cross-section shape and extending in a single direction over the substrate."
• Petitioner also proposed a construction for "gate electrode" as "a portion of a conductive shape in the gate layer that extends over and parallel with a diffusion region to form a transistor gate," arguing it was consistent with the specification and conventional CMOS technology.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 2, 31-33, and 35 of the ’966 patent as unpatentable.