PTAB

IPR2019-01369

Universal Imaging Industries LLC v. Lexmark Intl Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Dynamic Address Changing for Slave Devices on a Shared Bus
  • Brief Description: The ’657 patent relates to a system for dynamically changing the address of a slave device, such as a printer cartridge, communicating with a master device on a shared bus. The system purports to enhance security by having both the master and slave devices independently generate a new, synchronized address using a common algorithm, avoiding the need to transmit the new address over the bus. The patent claims an address structure comprising a fixed bit portion and a variable bit portion.

3. Grounds for Unpatentability

Ground 1: Obviousness over Schön, I²C Spec/Vernon, and Robb - Claims 1-3, 9-11 are obvious over Schön in view of I²C Spec or Vernon, and further in view of Robb.

  • Prior Art Relied Upon: Schön (Patent 5,708,831), I²C Spec (Version 2.1 of the I²C-Bus Specification), Vernon (Patent 5,088,024), and Robb (Application # 2007/0236726).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of references teaches all limitations of the challenged claims. Schön was asserted to teach the core method of a master device on a shared bus commanding slave devices to generate new addresses. The sole feature added during prosecution to achieve allowance of the parent application—a slave address including a fixed and variable bit portion—was allegedly taught by both the I²C Spec (the "de facto world standard" for such buses) and Vernon. Finally, Robb was cited to show the obviousness of applying this known bus communication technology to the specific environment of a printer system with replaceable ink or toner cartridges.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine these references because they address similar problems in the same field of shared bus communication. A POSITA implementing Schön’s address generation method would naturally look to the industry-standard I²C Spec or a similar protocol like Vernon for address formatting. Robb provided the explicit motivation to apply such a system to a printer, a common and predictable application for embedded systems.
    • Expectation of Success: The combination involved applying well-known address generation techniques with standard bus protocols in a conventional setting (a printer). Petitioner argued this would have been a straightforward implementation with a high expectation of success.

Ground 2: Obviousness over Mayer, I²C Spec/Vernon, and Robb - Claims 1-3, 9-11 are obvious over Mayer in view of I²C Spec or Vernon, and further in view of Robb.

  • Prior Art Relied Upon: Mayer (Patent 7,506,086), I²C Spec (Version 2.1 of the I²C-Bus Specification), Vernon (Patent 5,088,024), and Robb (Application # 2007/0236726).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative to Ground 1, substituting Mayer for Schön as the primary reference. Petitioner argued Mayer also discloses a master/slave communication system where slave devices use an internal number generator to create new identification codes (addresses) upon command from the master. As in Ground 1, I²C Spec or Vernon were relied upon to supply the teaching of an address with a fixed and variable bit portion, and Robb was used to place the invention in the context of a printer cartridge.
    • Motivation to Combine: The motivation was analogous to Ground 1. A POSITA would combine Mayer's method for dynamic address generation with the standard address formatting disclosed in I²C Spec or Vernon to create a robust addressing system. Applying this known technique to the printer environment taught by Robb was presented as a simple and predictable design choice.
    • Expectation of Success: As with the Schön combination, Petitioner argued that combining these established technologies for their intended purposes would have been routine for a POSITA, with a correspondingly high expectation of success.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 4-8 and 12-15 (Grounds 2 and 4 in the petition). These grounds were based on the primary combinations of Schön/Mayer, I²C Spec/Vernon, and Robb, but added a collection of "Pseudorandom Number Generator References" (including Maxfield, Kerl, Golomb, and Mano). These additional references were argued to teach the specific implementation details recited in the dependent claims, such as using a shift register (specifically a Linear Feedback Shift Register), non-volatile memory for storing a default address (a "seed"), and other logic for pseudorandom number generation. Petitioner argued a POSITA would have found it obvious to implement the "random" address generators of Schön or Mayer using these well-known techniques.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-15 of Patent 8,386,657 as unpatentable.