Advanced Micro Devices Inc v. Aquila Innovations Inc

1. Case Identification

• Case #: IPR2019-01526
• Patent #: 6,895,519
• Filed: September 13, 2019
• Petitioner(s): Advanced Micro Devices, Inc.
• Patent Owner(s): Aquila Innovations, Inc.
• Challenged Claims: 1-11

2. Patent Overview

• Title: System and Method for Controlling Clock Frequency for CPU and Peripheral Devices
• Brief Description: The ’519 patent describes a large-scale integration (LSI) system, such as a System-on-Chip (SoC), capable of dynamic clock control. The system uses software, including a "clock control library" and an application program, to manage transitions between different ordinary and special operation modes to conserve power.

3. Grounds for Unpatentability

Ground 1: Claims 1, 7, 10, and 11 are obvious over Ober in view of Nakazato.

• Prior Art Relied Upon: Ober (Patent 6,665,802) and Nakazato (Patent 6,681,336).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ober disclosed the core hardware of claim 1: a "system LSI" (an SoC) with a CPU, memory, a clock generation circuit, and a system control circuit (power manager) capable of switching between ordinary operation modes (e.g., normal mode with clock division) and special power-saving modes (IDLE, SLEEP) by writing to a register. However, Ober was vague on how software would control clock frequency during normal operation. Nakazato supplied this missing element, teaching a "power-saving driver" (the claimed "clock control library") and a user-facing "power-saving utility" (the claimed "application program") that allow a user to select a CPU speed, which then causes the driver to write to a register to adjust the CPU clock frequency.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) implementing Ober's power management system would need to determine how and when to adjust CPU clock frequency during normal operation. Since both Ober and Nakazato address power management via CPU frequency adjustment, a POSITA would have been motivated to combine Nakazato's well-defined software control method with Ober's hardware architecture to create a complete, functional system.
  • Expectation of Success: Success was predictable because both systems operate on the same principle: software writing a value to a hardware register to control clock speed. Integrating Nakazato's driver into Ober's system to control its existing clock control registers was a straightforward application of known software control techniques to a known hardware configuration.

Ground 2: Claims 2-6 are obvious over Ober and Nakazato, in further view of Cooper and Windows ACPI.

• Prior Art Relied Upon: Ober (Patent 6,665,802), Nakazato (Patent 6,681,336), Cooper (Patent 6,823,516), and Windows ACPI (“Draft ACPI Driver Interface Design Notes and Reference,” Microsoft, 1998).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground 1 to address dependent claims requiring a "plurality of libraries" and a "main library." Petitioner argued that Nakazato's driver was proprietary and would limit compatibility. To create a more versatile system, a POSITA would turn to a standardized interface like the Advanced Configuration and Power Interface (ACPI). Cooper disclosed using numerous ACPI objects (the claimed "plurality of libraries") for processor performance control. The Windows ACPI document, a well-known reference for the dominant operating system of the time, described the Windows ACPI driver (the claimed "main library") which provides an interface for other software to access and control ACPI functions. This main library is written in C, satisfying further dependent claims.
  • Motivation to Combine: A POSITA would recognize that a proprietary driver like Nakazato's limits a system's applicability. To ensure broad compatibility with various operating systems and applications, the POSITA would be motivated to adopt a widely implemented standard like ACPI. This would lead them to references like Cooper and Windows ACPI to understand how to implement a standardized, library-based control system for the Ober/Nakazato hardware and software combination.
  • Expectation of Success: A POSITA would have reasonably expected success in modifying Nakazato's driver to use the standard ACPI interface described in Windows ACPI to control the processor, as this involved replacing a proprietary control method with a well-documented, standardized one designed for that exact purpose.

Ground 3: Claims 8 and 9 are obvious over Ober and Nakazato, in further view of Doblar.

• Prior Art Relied Upon: Ober (Patent 6,665,802), Nakazato (Patent 6,681,336), and Doblar (Patent 6,516,422).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses claim 8, which adds a phase-locked loop (PLL) that receives a "plurality of standard clocks." Petitioner asserted that while Ober's clock generation circuit included a PLL, it was only shown receiving a single clock source. Doblar addressed the critical problem of system clock failure, teaching a redundant clock architecture to improve system uptime. Doblar's circuit used a PLL that received two standard clock inputs and could switch between them if one failed. Claim 9's requirement for a 32.768 kHz clock was met because this was a common, standard frequency for real-time clocks, and Ober disclosed a 32 kHz crystal.
  • Motivation to Combine: A POSITA would understand that the system clock is a critical component whose failure would disable the entire system described in Ober. To mitigate this known risk, the POSITA would be motivated to seek solutions for clock redundancy. Doblar directly addressed this problem by providing a PLL-based circuit for seamless switching between multiple clock sources, making it an obvious modification to improve the reliability of Ober's system.
  • Expectation of Success: The proposed modification was a simple substitution of one known element (Ober's single-input PLL) for another known element (Doblar's dual-input, redundant PLL) to achieve the predictable result of increased system reliability.

4. Key Claim Construction Positions

• "system LSI": Petitioner proposed the construction "a single integrated chip, which has a CPU, memory, and I/O capability," arguing this was consistent with the patent's specification and the understanding of a POSITA.
• "a clock control library for controlling a clock frequency transition...": For the purposes of the IPR, Petitioner adopted the Patent Owner's proposed construction from a co-pending litigation: "software that controls the change in the frequency of the clock signals in the ordinary operation modes."
• "principal constituents of said central processing unit": Petitioner proposed the construction "the processor cores but not circuitry responsible for responding to inputs, such as peripheral devices, or interrupts," arguing this was supported by explicit exclusions in the ’519 patent's specification.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-11 of the ’519 patent as unpatentable.