PTAB

IPR2019-01527

Advanced Micro Devices Inc v. Polaris Innovations Ltd

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Apparatus and Method for Generating a Transmit Signal
  • Brief Description: The ’526 patent relates to an apparatus for improving power efficiency and data integrity in signal transmission. It discloses combining data-bus inversion (DBI) with error-correction codes (ECC), where the key claimed feature is the generation of check information that depends on both the data bits and the DBI indicator bit.

3. Grounds for Unpatentability

Ground 1: Obviousness over Iglesia and Sridhara - Claims 1, 9-13, 24, and 25 are obvious over Iglesia in view of Sridhara.

  • Prior Art Relied Upon: Iglesia (Patent 6,490,703) and Sridhara (Srinivasa R. Sridhara & Naresh R. Shanbhag, Coding for System-on-Chip Networks: A Unified Framework, IEEE Transactions on VLSI Systems, 2005).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Iglesia disclosed a system architecture for performing both DBI and ECC, including breaking data into chunks to improve power savings. However, Iglesia did not explicitly teach protecting the DBI indicator itself with the ECC. Sridhara was argued to fill this gap by disclosing a framework for a joint DBI and ECC scheme where the generated check information (parity bits) explicitly depends on both the original data bits and an "invert bit" (the indicator).
    • Motivation to Combine (for §103 grounds): A person of ordinary skill in the art (POSITA) starting with Iglesia’s system would seek to improve its error protection by ensuring the DBI indicator bit was also protected, leading them to Sridhara’s teachings. Conversely, a POSITA implementing Sridhara’s theoretical framework would look to a practical architecture like Iglesia’s. Additional motivation was cited from Sridhara’s disclosure that its method achieves a significant 21%-33% reduction in encoder delay.
    • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success because combining the references involved applying fundamental, well-understood techniques (DBI and Hamming codes) and substituting one known element (Sridhara's framework) for another (Iglesia's separate generators) to achieve a predictable result.

Ground 2: Obviousness over Iglesia, Sridhara, and Uya - Claims 2, 3, 5, 14, 15, 17, and 21-23 are obvious over Iglesia and Sridhara, further in view of Uya.

  • Prior Art Relied Upon: Iglesia (’703 patent), Sridhara (2005 IEEE publication), and Uya (Patent 4,417,161).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Iglesia/Sridhara combination to address dependent claims related to the processor’s operation. Specifically, claim 2 recites determining a "first check information" assuming a first state of the indicator, and then modifying it if the indicator's actual state is different. Petitioner contended that Sridhara taught this functionality through a conditional inverter that functions as a logical XOR gate. While Sridhara described the function, Uya was argued to disclose a specific, transistor-level implementation of a low-power XOR gate circuit that performs the exact logic required.
    • Motivation to Combine (for §103 grounds): A POSITA implementing Sridhara's conditional inverter logic would be motivated to find a known, efficient circuit design. Uya was presented as an attractive solution because it disclosed an XOR gate with fewer transistors than conventional designs, which is highly desirable for reducing power consumption in large-scale integrated circuits.
    • Expectation of Success (for §103 grounds): Uya explicitly stated that its XOR gate works well in large-scale integrated circuits, providing a clear expectation of success when incorporating its well-known circuit into the system proposed by the combination of Iglesia and Sridhara.

Ground 3: Obviousness over Liu and Iglesia - Claims 1, 9, 12, 24, and 25 are obvious over Liu in view of Iglesia.

  • Prior Art Relied Upon: Liu (Patent 7,102,544) and Iglesia (’703 patent).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented an alternative primary reference to Sridhara. Petitioner argued that Liu, like Sridhara, disclosed a system that determines check information (a parity bit) based on both the data bits and a status bit (the indicator). This taught the core feature of the challenged independent claims. The argument then turned to dependent claims (e.g., claim 9) requiring the data to be broken into portions with separate indicators. Liu taught using a single indicator for an entire data word, while Iglesia taught splitting a data word into chunks and using multiple "flip bits" (indicators) to achieve greater power savings.
    • Motivation to Combine (for §103 grounds): A POSITA would be motivated to improve the power-saving aspect of Liu's system. This would lead them to Iglesia, which explicitly taught that greater power savings can be obtained by using multiple indicators for separate chunks of data. Combining the teachings would involve applying Liu's error protection scheme on a per-chunk basis, as enabled by Iglesia's architecture.
    • Expectation of Success (for §103 grounds): The combination involved applying a known technique (chunk-based DBI from Iglesia) to improve a similar device (Liu's DBI/ECC system) in a predictable way to achieve a known goal (reduced power consumption).

  • Additional Grounds: Petitioner asserted a fourth ground that Liu alone anticipates claims 1, 12, 24, and 25 under 35 U.S.C. §102, arguing that Liu taught every element of these independent claims.

4. Key Claim Construction Positions

  • Petitioner argued that the term “checksum,” which appeared in claims 5-11 and 17-23, should be construed as “a plurality of ECC bits.” This construction was asserted to be supported by the patent’s specification, which described a checksum as comprising multiple ECC bits and referred to checksums in the context of Hamming code, which uses multiple bits. This construction was important to the Petitioner’s arguments as the prior art, including Sridhara and Iglesia, disclosed generating multiple parity or ECC bits.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-3, 5, 9-15, 17, and 21-25 of Patent 8,117,526 as unpatentable.