Sony Mobile Communications USA Inc v. Super Interconnect Technologies LLC

1. Case Identification

• Case #: IPR2019-01592
• Patent #: 7,627,044
• Filed: September 16, 2019
• Petitioner(s): Sony Mobile Communications (USA) Inc.
• Patent Owner(s): Super Interconnect Technologies LLC
• Challenged Claims: 1-3, 8-9, 13-14, and 19

2. Patent Overview

• Title: Clock-Edge Modulated Serial Link With DC-Balance Control
• Brief Description: The ’044 patent describes a signal transmitter and receiver system that multiplexes clock, data, and control signals for transmission over a single direct current (DC) balanced differential channel. The system uses pulse-width modulation (PWM) of a clock signal to incorporate "direct current balancing control signals" to maintain DC balance.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Ozawa - Claims 1-3, 8-9, and 13 are anticipated under 35 U.S.C. §102 or obvious under §103 over Ozawa.

• Prior Art Relied Upon: Ozawa (Application # 2005/0286643).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Ozawa, which discloses a system for transmitting clock, data, and control information over a single serialized data channel, taught every limitation of the challenged claims. Specifically, Ozawa described a transmitter and receiver communicating over a single DC-balanced differential channel using a twisted cable pair. Petitioner contended that Ozawa's method of using the current running disparity (CRD) to encode control information and either reduce or increase the pulse width of the signal to maintain DC-balance inherently disclosed the ’044 patent’s central feature: a clock signal pulse-width modulated to incorporate "direct current balancing control signals." The mapping extended to the receiver claims, where Ozawa's receiver was described as recovering the clock and DC-balancing control information from the PWM signal.
  • Motivation to Combine (for §103 grounds): While primarily an anticipation ground, Petitioner argued in the alternative that all claimed features were present in Ozawa, and combining them as claimed would have been an obvious design choice for a person of ordinary skill in the art (POSITA).
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Ozawa itself demonstrated a functional system incorporating all the relevant technologies.

Ground 2: Obviousness over Kim in view of Ozawa - Claims 1-3, 8-9, 13-14, and 19 are obvious over Kim in view of Ozawa.

• Prior Art Relied Upon: Kim (Application # 2002/0181608) and Ozawa (Application # 2005/0286643).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Kim disclosed a differential signaling system that multiplexed clock and data signals over a single, DC-balanced channel using PWM, meeting most claim limitations. Kim's encoder used an "encoding scheme [that] is direct current (DC) balanced," but did not detail the specific mechanism. Ozawa was argued to supply this missing detail. Ozawa taught using CRD to actively vary the pulse width of a signal to maintain DC balance, which Petitioner argued was the specific type of "direct current balancing control signals" claimed in the ’044 patent.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Kim's PWM signaling system with Ozawa's explicit DC-balancing technique because both references were directed to the same technical problem: transmitting serialized data over a single DC-balanced channel for a display interface. A POSITA would look to a reference like Ozawa to implement the general "DC balancing" mentioned in Kim, seeking a known and effective method to ensure signal integrity.
  • Expectation of Success (for §103 grounds): Success was expected because it involved applying a known DC-balancing technique (from Ozawa) to a compatible PWM signaling system (from Kim) to achieve the predictable benefit of improved DC balance.

Ground 3: Obviousness over Chen in view of IEEE-1394b - Claims 1-3, 8-9, and 13 are obvious over Chen in view of IEEE-1394b.

• Prior Art Relied Upon: Chen (a 2001 IEEE Journal article) and IEEE-1394b (a 2002 IEEE standard).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chen taught a "PWM transceiver" that merged clock and data channels into a single channel using PWM to reduce pin count. Chen suggested using a differential channel like the IEEE 1394a serial bus. While Chen's system used PWM, it did not explicitly teach DC-balancing control signals. Petitioner asserted that the IEEE-1394b standard, an amendment to the standard mentioned in Chen, supplied the missing DC-balancing element. IEEE-1394b explicitly taught using 8B/10B encoding to enforce DC balance by using control characters and running disparity to maintain, increase, or decrease the disparity, which Petitioner equated to the claimed "direct current balancing control signals."
  • Motivation to Combine (for §103 grounds): A POSITA would combine these references because IEEE-1394b was a direct evolution of the technology suggested by Chen. To address the known problem of DC balance over longer distances—a limitation of the earlier standard—a POSITA implementing Chen's system would naturally look to the improved IEEE-1394b standard to enhance signal integrity, a stated goal of both references.
  • Expectation of Success (for §103 grounds): A POSITA would expect success in applying the well-defined DC-balancing protocol of IEEE-1394b to Chen's PWM system to predictably improve performance.
• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Ozawa with Kim to add a voltage-mode driver and bidirectional transfer capability (Ground 3), and adding Kim's teachings to the Chen/IEEE-1394b combination (Ground 6).

4. Key Claim Construction Positions

• Petitioner argued that the preamble phrase "[a] battery powered computing device" in claims 13, 14, and 19 should be construed as non-limiting. The argument was that the preamble merely stated an intended use for a structurally complete signal transmitter/receiver and was not relied upon during prosecution to distinguish the invention over the prior art.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise its discretion to deny institution under §325(d). Although the Ozawa and Chen references were cited during the original prosecution, Petitioner contended they were never substantively analyzed or applied against the claims. Ozawa was mentioned only in a brief summary in an office action, and Chen was only listed in an IDS, with no indication that the Examiner considered the specific teachings now relied upon concerning "direct current balancing control signals."

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-3, 8-9, 13-14, and 19 of the ’044 patent as unpatentable.