Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00112
• Patent #: 6,366,522
• Filed: November 15, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-4, 6-8, 25, and 28

2. Patent Overview

• Title: Power Management for Integrated Circuits using Dynamic Voltage and Frequency Scaling
• Brief Description: The ’522 patent relates to a power-efficient integrated circuit that uses Dynamic Voltage and Frequency Scaling (DVFS). The system dynamically adjusts its clock frequency and supply voltage based on a "processing transfer characteristic" of the hardware and the "processing requirements" of a software application to conserve power.

3. Grounds for Unpatentability

Ground I: Obviousness over Borkar, Bland, Wilcox, and Ackermann - Claims 1-4, 6-7, and 28 are obvious over the combination.

• Prior Art Relied Upon: Borkar (Patent 6,484,265), Bland (Patent 5,614,869), Wilcox (Patent 5,481,178), and Ackermann (Patent 6,137,280).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Borkar taught the core DVFS system of claim 1, including a processor, memory, and control circuitry that adjusts clock and voltage signals based on application demands and processor characteristics. Petitioner contended that Borkar’s high-level disclosure was enabled by other references disclosing conventional components. Bland supplied the teaching of a standard Phase Lock Loop (PLL) receiving a reference clock, which Petitioner argued would be an inherent feature of Borkar's PLL. Wilcox disclosed a well-known boost regulator that regulates a supply from a "power source and an inductance," satisfying a key limitation added to the ’522 patent claims during re-examination. Finally, Ackermann taught using a programmable resistive divider to control the output voltage of a regulator, providing a known method for implementing Borkar’s required power supply control signal.
  • Motivation to Combine: A POSITA implementing Borkar's conceptual DVFS system would combine these references to supply well-known components for the system's functional blocks. Borkar's system required a PLL and a voltage regulator, and Bland and Wilcox provided conventional, suitable designs. To implement Borkar's requirement for a controllable voltage supply, a POSITA would look to known control methods like the programmable divider taught by Ackermann.
  • Expectation of Success: A POSITA would have a reasonable expectation of success as the combination involved implementing a high-level system with well-known, off-the-shelf circuit designs that were common in the art for their respective functions.

Ground II: Obviousness over Borkar, Bland, Wilcox, Ackermann, and Horden - Claim 3 is obvious over the combination.

• Prior Art Relied Upon: The combination from Ground I, plus Horden (Patent 5,812,860).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground incorporated the arguments for claim 3 from Ground I and added Horden to further support the "known executional requirements" limitation. Claim 3 requires a "training module" to determine settings based on requirements like "millions of instructions per second (MIPS)." While Borkar taught using general "rating instructions," Horden explicitly taught using MIPS as an "objective measure of processor need" for an application to control voltage and frequency.
  • Motivation to Combine: Since Borkar did not specify the exact nature of its "rating instructions," a POSITA would look to similar power-management patents for concrete examples. Horden, assigned to the same entity as Borkar (Intel), described a similar system and provided MIPS as a specific, objective metric, making it an obvious choice to implement Borkar's more general teaching.

Ground III: Obviousness over Borkar, Bland, Wilcox, Ackermann, and Jones - Claim 25 is obvious over the combination.

• Prior Art Relied Upon: The combination from Ground I, plus Jones (Patent 5,764,007).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Jones to address dependent claim 25, which required the regulator's inductance to be an "external inductance." The primary combination taught a regulator with an inductance (from Wilcox), but Jones explicitly disclosed a single-chip integrated circuit with a boost regulator where the inductor was an external component.
  • Motivation to Combine: Petitioner argued it was common practice at the time that inductors for on-chip regulators were typically external due to their physical size. Jones provided an explicit example of this standard design choice. A POSITA implementing the Wilcox regulator in Borkar's integrated circuit would have been motivated to place the inductor externally as a standard, practical implementation.

Ground IV: Obviousness over Borkar, Bland, Wilcox, Ackermann, and Hanington - Claim 8 is obvious over the combination.

• Prior Art Relied Upon: The combination from Ground I, plus Hanington (a 1999 IEEE publication).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed dependent claim 8, which required that "multiple supplies...are produced from the system clock." While the primary combination taught a switching regulator (Wilcox) that a POSITA would understand requires a clock, Hanington explicitly disclosed a boost regulator synchronized by a 10 MHz system clock.
  • Motivation to Combine: If the primary combination were seen as not explicitly teaching the use of a system clock for the regulator, a POSITA would look to conventional boost regulator designs like Hanington's. A POSITA would combine this with Borkar's system, which already generated a system clock via its PLL, to drive the Wilcox regulator, as this was a conventional and predictable design choice.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) would be inappropriate. The ’522 patent was part of a large, multi-venue litigation, and the PTAB provided a more efficient and technically expert forum than a district court jury for the complex obviousness arguments presented. Petitioner asserted that although a trial date was set in a co-pending district court case, an inter partes review (IPR) could reach a final written decision more quickly than the district court could reach a final, appealable judgment, and the petition was filed diligently with months remaining before the statutory bar.

5. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-4, 6-8, 25, and 28 of the ’522 patent as unpatentable.