Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00113
• Patent #: 6,366,522
• Filed: November 15, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 9-11, 13-15, 30-31, and 34

2. Patent Overview

• Title: Dynamic Voltage and Frequency Scaling
• Brief Description: The ’522 patent discloses a method for controlling power consumption in an integrated circuit using Dynamic Voltage and Frequency Scaling (DVFS). The method involves dynamically adjusting a system clock frequency and a supply voltage based on the "processing transfer characteristic" of a computation engine and the "processing requirements" of a software application being executed.

3. Grounds for Unpatentability

Ground 1: Claims 9-11, 13-14, and 34 are obvious over Borkar, Bland, Wilcox, and Ackermann

• Prior Art Relied Upon: Borkar (Patent 6,484,265), Bland (Patent 5,614,869), Wilcox (Patent 5,481,178), and Ackermann (Patent 6,137,280).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination disclosed every element of the challenged claims. Borkar, the primary reference, taught the core DVFS method of controlling power consumption in an integrated circuit by adjusting clock frequency and supply voltage in response to application demands and processor performance parameters. Borkar’s system included a processor, voltage control circuitry, and a phase-locked loop (PLL), but lacked specific implementation details. The secondary references were argued to supply these known details. Bland taught a conventional programmable PLL that generates a system clock from a reference clock, a detail not explicit in Borkar. Wilcox disclosed a power-efficient step-up (boost) converter, a well-known voltage regulator that operates from a power source and an inductance, which Petitioner contended was an obvious choice to implement Borkar’s on-chip supply generating circuitry. Finally, Ackermann taught using a programmable resistive divider (a digital potentiometer) to control the output of a DC-to-DC converter, providing a known method for making the voltage regulator from Wilcox adjustable in response to Borkar’s power supply control signal.
  • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine these references to achieve a predictable, power-efficient system. A POSITA implementing Borkar's high-level DVFS scheme would naturally turn to well-known, standard components to realize the system. This would include using a conventional PLL design like Bland's, selecting a suitable power-efficient regulator like the Wilcox boost converter for battery-operated devices, and employing a standard control mechanism like Ackermann's programmable divider to make the voltage output adjustable as required by Borkar.
  • Expectation of Success: A POSITA would have had a high expectation of success because the combination involved integrating known components, each performing its intended function, to implement Borkar's established DVFS framework. The result would have been the predictable aggregation of known elements.

Ground 2: Claims 11, 15, 30, and 31 are obvious over the primary combination in view of Horden, Hanington, or Jones

• Prior Art Relied Upon: The combination from Ground 1, plus one of the following for specific claims: Horden (Patent 5,812,860), Jones (Patent 5,764,007), or Hanington (a 1999 IEEE publication).
• Core Argument for this Ground:
  • Prior Art Mapping: These grounds addressed dependent claims by adding one additional reference to the main combination from Ground 1 to disclose specific features.
    • Horden (for claim 11): To meet the limitation of determining processing requirements based on "millions of instructions per second (MIPS)," Petitioner cited Horden. Horden taught a similar power-efficient system where an "objective measure of processor need" for an application could explicitly be MIPS.
    • Jones (for claims 30-31): To show the obviousness of using an "external inductance," Petitioner relied on Jones. Jones described a single-chip integrated circuit with a boost converter where the inductor was an external component. Petitioner argued this was a common and necessary design choice at the time for inductors, which were too large to be integrated on-chip.
    • Hanington (for claim 15): To demonstrate that regulating multiple supplies from a system clock was obvious, Petitioner pointed to Hanington. Hanington explicitly disclosed using a system clock (e.g., a 10MHz clock) to synchronize and control the operation of a boost converter, which would be a natural way to implement the Wilcox regulator within Borkar’s clock-based system.
  • Motivation to Combine: The motivation for adding each reference was presented as an obvious design choice or implementation detail. A POSITA seeking a concrete metric for Borkar's abstract "processor resource intensiveness" would have found MIPS as taught by Horden. When building the regulator, using an external inductor as shown in Jones was a standard practice. Similarly, using the main system clock to drive the switching regulator, as taught by Hanington, was a conventional and logical design choice.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial of institution under 35 U.S.C. §314(a). It contended that the inter partes review (IPR) forum was more efficient and better suited for the complex, multi-reference obviousness grounds than the co-pending district court litigation. Petitioner asserted that the PTAB’s technical expertise was critical for adjudication. It also argued that the district court trial schedule was uncertain and that a Final Written Decision (FWD) from the IPR would likely issue before a final, appealable judgment from the court, thus promoting efficiency and avoiding duplicative efforts.

5. Relief Requested

• Petitioner requested institution of IPR and cancellation of claims 9-11, 13-15, 30-31, and 34 of the ’522 patent as unpatentable.