Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00114
• Patent #: 6,366,522
• Filed: November 15, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 16-18, 20-22, 36-38

2. Patent Overview

• Title: Power Management for Integrated Circuits
• Brief Description: The ’522 patent relates to a system for controlling power consumption in integrated circuits using Dynamic Voltage and Frequency Scaling (DVFS). The technology dynamically adjusts a processor’s clock frequency and supply voltage based on the "processing transfer characteristic" of the circuit and the "processing requirements" of a running application.

3. Grounds for Unpatentability

Ground I: Obviousness of Claims 16-18, 20-21, and 37-38 over Borkar, Bland, Wilcox, and Ackermann

• Prior Art Relied Upon: Borkar (Patent 6,484,265), Bland (Patent 5,614,869), Wilcox (Patent 5,481,178), and Ackermann (Patent 6,137,280).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of these references taught every limitation of the challenged claims. Borkar, the primary reference, disclosed the foundational DVFS concept of an integrated circuit that adjusts its own clock frequency and supply voltage to balance power consumption and performance. It taught a processing module with memory that determines voltage and clock settings based on transistor speed characteristics and the demands of a running application. Petitioner contended that Bland was used to explicitly supply the teaching of a conventional Phase-Locked Loop (PLL) that produces a system clock from a reference clock, a common feature Borkar’s system would require. Wilcox was cited to provide a specific, well-known implementation for Borkar’s generic voltage regulator: a boost converter that regulates a supply from a "power source and an inductance," a limitation added to the claims during a prior re-examination. Finally, Ackermann was introduced to teach how to make the voltage regulator programmable. Ackermann disclosed using a digital potentiometer to form a programmable resistive divider, which allows a microprocessor to precisely control the regulator's output voltage, thereby enabling the software-controlled adjustments described in Borkar.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to create an improved DVFS system. A POSITA implementing Borkar’s DVFS scheme would naturally look to well-known components like Bland’s PLL for clock generation and Wilcox’s boost regulator for voltage supply, particularly in battery-operated devices where efficiency is critical. To enable Borkar’s software-based control over the supply voltage, a POSITA would have been motivated to incorporate Ackermann’s programmable divider circuit into Wilcox’s regulator design.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination involved integrating standard, well-understood circuit components (PLLs, boost regulators, programmable dividers) in a predictable manner to achieve the known benefits of DVFS.

Ground II: Obviousness of Claim 18 over the Ground I Combination and Horden

• Prior Art Relied Upon: Borkar, Bland, Wilcox, Ackermann, and Horden (Patent 5,812,860).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground specifically targeted claim 18, which adds the requirement that the "known executional requirements" of an application include "millions of instructions per second (MIPS)." While Borkar taught using "rating instructions" to quantify an application's processing needs, Petitioner argued it did not specify the metric. Horden, which addresses a similar power-saving problem, explicitly disclosed using MIPS as an objective measure of processor need to determine appropriate voltage and frequency levels.
  • Motivation to Combine: A POSITA implementing Borkar’s system would seek a concrete, objective metric for the "rating instructions" and would have been motivated to adopt Horden’s use of MIPS. The motivation was particularly strong as both Borkar and Horden were assigned to Intel, and a POSITA would look to related art from the same assignee.

Ground III: Obviousness of Claim 36 over the Ground I Combination and Jones

• Prior Art Relied Upon: Borkar, Bland, Wilcox, Ackermann, and Jones (Patent 5,764,007).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addressed dependent claim 36, which requires the regulator’s inductance to be an "external inductance." Petitioner asserted that while Wilcox’s boost converter required an inductor, it did not specify its location. Jones was cited for its disclosure of an integrated circuit with an on-chip boost regulator that explicitly used an external inductor.
  • Motivation to Combine: A POSITA would have been motivated to implement the inductor in the Wilcox regulator as an external component because it was common practice for integrated voltage regulators at the time. The required inductance values were typically too large for on-chip integration, making an external component the obvious and standard design choice, as exemplified by Jones.

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground IV) against claim 22 based on the core combination plus Hanington (a 1999 article). Hanington was cited for its teaching of using a system clock to synchronize a boost converter when regulating multiple unique supplies.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise discretionary denial under 35 U.S.C. §314(a) based on the parallel district court litigation. Petitioner contended that an inter partes review (IPR) was a more efficient and expert forum for adjudicating the complex, multi-reference obviousness grounds compared to a jury trial in the Western District of Texas.
• Petitioner further argued that uncertainty surrounding the district court trial schedule and the potential for post-trial motions meant a Final Written Decision (FWD) from the IPR could issue before a final appealable judgment, thereby promoting efficiency and conserving judicial resources. The petition was also filed three months prior to its statutory deadline, demonstrating diligence.

5. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 16-18, 20-22, and 36-38 of Patent 6,366,522 as unpatentable under 35 U.S.C. §103.