Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00141
• Patent #: 6,633,187
• Filed: November 22, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1 and 12

2. Patent Overview

• Title: Power on Reset Techniques for an Integrated Circuit Chip
• Brief Description: The ’187 patent discloses a method for enabling a stand-alone integrated circuit (IC) using a "power-on-reset" (POR) sequence. The method is directed at ICs that include an on-chip power converter which requires a clock signal to generate a stable supply voltage for the chip's digital circuitry.

3. Grounds for Unpatentability

Ground 1: Obviousness over Page, Stratakos, and Bujanos - Claims 1 and 12 are obvious over Page in view of Stratakos and Bujanos.

• Prior Art Relied Upon: Page (Patent 6,980,037), Stratakos (a 1999 Ph.D. thesis on DC-DC conversion), and Bujanos (Patent 5,949,227).
• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that the primary reference, Page, discloses the foundational elements of the challenged claims. Page teaches a POR method for an IC with an on-chip switched converter. This method includes establishing an idle state by inhibiting clocks upon power application, activating a phase-locked loop (PLL) to generate a master clock signal, using that clock to drive the switched converter to generate an internal supply voltage, and releasing the clock hold to enable chip functionality only after the internal supply has stabilized. Petitioner contended this maps to most limitations of claim 1.

    To supply the remaining limitations, Petitioner turned to Stratakos and Bujanos. Petitioner argued Stratakos teaches key details of the converter’s control circuitry not fully elaborated in Page. Specifically, Stratakos teaches that switching regulators commonly require a stable reference voltage for regulation and that band-gap references are often used for this purpose due to their temperature stability. This, Petitioner asserted, teaches the limitation of using a band-gap reference in generating power converter regulation signals.

    Finally, Petitioner argued Bujanos teaches enabling a band-gap reference via an "enable signal" to conserve power by keeping the reference deactivated when not needed. Petitioner mapped this teaching to the limitation of enabling the band-gap reference upon assertion of a power enable signal, completing the combination for claim 1. Dependent claim 12, which adds the IC structure corresponding to the method of claim 1, was argued to be obvious for the same reasons.

  • Motivation to Combine: Petitioner asserted a strong motivation for a person of ordinary skill in the art (POSITA) to combine Page and Stratakos. Page expressly references a conference paper by Dr. Stratakos on "High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications"—the same subject as his Ph.D. thesis—when discussing its switched converter. Petitioner argued this reference would have directly led a POSITA to Stratakos’s work to implement or optimize the control circuitry for Page’s converter, including the use of a band-gap reference.

    The motivation to further combine Bujanos stemmed from the shared goal of power efficiency. Petitioner noted that Page’s IC is designed for low power consumption and Stratakos’s work is directed at portable applications where power savings are critical. A POSITA, seeking to enhance the power efficiency of the Page/Stratakos circuit, would combine the teachings of Bujanos to add an enable/disable feature to the band-gap reference, a known technique for reducing power consumption.

  • Expectation of Success: Petitioner argued a POSITA would have a reasonable expectation of success. The combination involved integrating well-known, compatible components for their predictable functions: using a standard band-gap reference (from Stratakos) to provide a stable voltage for a switching regulator (in Page) and adding a conventional enable circuit (from Bujanos) to conserve power. The implementation was presented as a straightforward application of conventional circuit design principles.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) would be inappropriate. The petition asserted that an inter partes review (IPR) is a more efficient and expert forum for the complex, multi-reference obviousness arguments presented than a district court jury trial. Petitioner highlighted the PTAB’s technical expertise in electrical engineering. It also noted uncertainty in the co-pending district court litigation schedule and argued that a Final Written Decision (FWD) could issue before a final, appealable judgment from the court, thus promoting efficiency and avoiding conflicting outcomes. Petitioner also stated it was diligent in filing the petition well before the one-year statutory bar.

5. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1 and 12 of the ’187 patent as unpatentable.