Intel Corp v. XMTT Inc

1. Case Identification

• Case #: IPR2020-00144
• Patent #: 8,145,879
• Filed: November 13, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): XMTT, Inc.
• Challenged Claims: 1-38

2. Patent Overview

• Title: Computer Memory Architecture for Hybrid Serial and Parallel Computing Systems
• Brief Description: The ’879 patent relates to hybrid multiprocessor computing systems that execute programs using separate serial and parallel processing modes. The invention purports to provide a specific computer architecture and methods for coordinating transitions between these modes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Nakaya and Nakamura - Claims 1-3, 14, 15, 18, and 19 are obvious over Nakaya in view of Nakamura.

• Prior Art Relied Upon: Nakaya (Patent 5,978,830) and Nakamura (Application # 2003/0177273).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nakaya disclosed a hybrid computing system with serial and parallel processors that transition between modes, along with shared memory modules (“inter-processor data transfer areas”) for communication. However, Nakaya did not explicitly disclose a separate, private memory for each processor. Nakamura disclosed improving multiprocessor systems by adding local cache memories for each processor’s dedicated use to increase processing speed. The combination of Nakaya’s hybrid system with Nakamura’s local cache memories allegedly rendered the core architectural elements of independent claim 1 obvious.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Nakamura's local cache memories into Nakaya’s processors to achieve faster processing, a well-known goal in computer architecture. Petitioner asserted the technologies were compatible and easily combined, as both were assigned to Hitachi and shared a common inventor.
  • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success because Nakaya and Nakamura describe similar multiprocessor systems with compatible shared memory architectures, making the integration of local caches straightforward.

Ground 2: Obviousness over Nakaya, Nakamura, and Koufaty - Claims 4, 5, and 13 are obvious over the combination of Nakaya, Nakamura, and Koufaty.

• Prior Art Relied Upon: Nakaya (Patent 5,978,830), Nakamura (Application # 2003/0177273), and Koufaty (a 1996 IEEE article, "Data Forwarding in Scalable Shared-Memory Multiprocessors").
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Nakaya/Nakamura combination to address claims reciting specific data transfer operations during mode transitions, such as transferring updated data and receiving acknowledgements. Petitioner contended that Koufaty taught data forwarding and prefetching techniques to reduce memory access latency. This included sending an "acknowledgement message" from a consumer processor back to the producer processor to confirm a data transfer.
  • Motivation to Combine (for §103 grounds): A POSITA would incorporate Koufaty's data transfer techniques into the Nakaya/Nakamura system to improve the speed and efficiency of data transfers during the synchronization process. Scheduling coordinated memory transfers, as taught by Koufaty, would reduce processor latency and allow subsequent processing to occur faster.
  • Expectation of Success (for §103 grounds): Success was expected because Koufaty’s techniques were complementary to the base system. Implementing Koufaty’s compiler-based instructions for data forwarding into Nakaya’s architecture, which already involved compiling programs into serial and parallel jobs, was argued to be a routine programming task.

Ground 3: Obviousness over Nakaya, Nakamura, Koufaty, and Vishkin - Claims 6-9, 16, and 20-38 are obvious over the combination of Nakaya, Nakamura, Koufaty, and Vishkin.

• Prior Art Relied Upon: Nakaya (Patent 5,978,830), Nakamura (Application # 2003/0177273), Koufaty (1996 IEEE article), and Vishkin (a 1998 ACM symposium article, "Explicit Multi-Threading (XMT) Bridging Models for Instruction Parallelism").

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addressed claims reciting specific "signals" and "commands" (e.g., "broadcast," "prefetch signal," "spawn command") for initiating parallel processing. Petitioner argued Vishkin disclosed an algorithm-driven approach to increasing parallelism using "spawn" and "join" commands to initiate and conclude multi-threaded processing. Vishkin also taught prefetching data prior to a spawn instruction to alleviate cache-miss penalties.
  • Motivation to Combine (for §103 grounds): A POSITA would add Vishkin's command set to the existing combination to further increase parallelism and processing speed, particularly during the transitions between serial and parallel modes. Nakaya’s system, where a serial processor controls synchronization, provided a natural framework for implementing Vishkin’s commands to manage the parallel processors.
  • Expectation of Success (for §103 grounds): The combination was argued to be a straightforward addition, as Vishkin’s command-based approach was designed to fit into existing multiprocessor architectures and would have required only routine compiler programming to implement within Nakaya's system.

• Additional Grounds: Petitioner asserted a fourth ground that claims 10-12 and 17 are obvious over Nakaya, Nakamura, and Vishkin, relying on similar motivations to combine these references to implement specific "spawn" and "join" command functionalities.

4. Key Claim Construction Positions

• "read-only memory": Petitioner argued this term required construction because the patent acted as its own lexicographer, defining it contrary to its plain and ordinary meaning.
  • Proposed Construction: "memory for a parallel processor that stores updated data generated by the parallel processor only when the updated data is already available to other parallel processors and/or a serial processor."
  • Rationale: The petition asserted that a POSITA would understand "read-only memory" as memory that cannot be updated. However, the ’879 patent specification explicitly described a scenario where the claimed "read-only memory" can be updated, but only after the updated data is first made available to other processors (e.g., stored in a shared memory). This construction was critical to mapping Nakamura's data coherency mechanism—which requires making data available to other processors before updating a local copy—to this claim limitation.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-38 of the ’879 patent as unpatentable.