Intel Corp v. XMTT Inc

1. Case Identification

• Case #: IPR2020-00145
• Patent #: 7,707,388
• Filed: November 13, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): XMTT, Inc.
• Challenged Claims: 1-39

2. Patent Overview

• Title: Computer Memory Architecture for Hybrid Serial and Parallel Computing Systems
• Brief Description: The ’388 patent relates to hybrid multiprocessor computing systems that operate in distinct serial and parallel processing modes. The technology purports to achieve coordinated execution through a claimed architecture comprising serial and parallel processors with associated memories and by managing data transfers during transitions between the two modes.

3. Grounds for Unpatentability

Ground 1: Obviousness over Nakaya, Nakamura, and Koufaty - Claims 1, 3, 12-14, 17, and 18 are obvious over Nakaya, Nakamura, and Koufaty.

• Prior Art Relied Upon: Nakaya (Patent 5,978,830), Nakamura (Application # 2003/0177273), and Koufaty (a 1996 IEEE journal article on data forwarding).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the base combination of Nakaya and Nakamura taught the core architecture of independent claim 1. Nakaya disclosed a hybrid processor system with serial and parallel processors that transition between modes and utilize a shared memory. Nakamura, when combined, supplied the claimed "serial memory" element by teaching the use of local cache memories for each processor in a similar multiprocessor system. Petitioner asserted that Koufaty provided the data transfer mechanisms recited in claim 1, such as forwarding updated data from the serial processor to parallel processors prior to a transition and receiving a corresponding acknowledgement to confirm the data was queued or committed.
  • Motivation to Combine: A POSITA would combine Nakamura's local cache memories with Nakaya's hybrid system to achieve faster processing, a common and predictable goal in the art. The motivation to further add Koufaty's techniques was to improve the efficiency and reduce the latency of Nakaya's synchronization process. Koufaty explicitly taught using data forwarding and prefetching as complementary techniques to move data to consumer processors before it is needed, which would directly benefit the transitions between serial and parallel modes in Nakaya.
  • Expectation of Success: Petitioner asserted a high expectation of success. Nakaya and Nakamura described similar multiprocessor architectures, were both assigned to Hitachi, and shared a common inventor, suggesting their technologies were compatible. Incorporating Koufaty's data transfer instructions into Nakaya's system would have been a straightforward compiler programming task, representing a predictable combination of prior art elements.

Ground 2: Obviousness over Nakaya, Nakamura, Koufaty, and Vishkin - Claims 2, 4-11, 15, 16, and 19-39 are obvious over Nakaya, Nakamura, Koufaty, and Vishkin.

• Prior Art Relied Upon: Nakaya (Patent 5,978,830), Nakamura (Application # 2003/0177273), Koufaty (a 1996 IEEE journal article), and Vishkin (a 1998 ACM symposium paper on multi-threading).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination in Ground 1, adding the teachings of Vishkin to address limitations in the remaining claims related to specific signals and commands for managing parallel processing. Petitioner argued that Vishkin supplied the explicit "spawn" and "join" commands for initiating and terminating multi-threaded parallel processing. For example, Vishkin's teaching of broadcasting a "spawn" command to initiate parallel threads was mapped to the "broadcast a first signal for substantially concurrent initiation of the parallel processing mode" in claim 2. Vishkin also taught prefetching data prior to a spawn instruction to reduce latency, aligning with the prefetching limitations in claims 4 and 5.
  • Motivation to Combine: A POSITA would combine Vishkin with the base system of Nakaya/Nakamura/Koufaty to implement a more efficient, algorithm-driven method for managing parallelism. While Nakaya described a system that transitions between serial and parallel jobs, it lacked the specific command structures for modern threaded processing. Vishkin provided an extended instruction set for this exact purpose, touting it as a way to further increase parallelism and efficiency. This provided a known, well-understood framework for managing the transitions already present in Nakaya.
  • Expectation of Success: Petitioner argued that success was reasonably expected because Vishkin explicitly stated its multi-threaded architecture would "fit naturally" with a variety of existing multiprocessor organizations. Implementing Vishkin's command set in Nakaya's system was described as a routine programming task with predictable outcomes, as it involved mapping Vishkin's commands onto the existing serial and parallel processing states in Nakaya.

4. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-39 of the ’388 patent as unpatentable.