Flex Logix Technologies Inc v. Konda Venkat

1. Case Identification

• Patent #: 8,269,523
• Filed: December 16, 2019
• Petitioner(s): Flex Logix Technologies, Inc.
• Patent Owner(s): Venkat Konda
• Challenged Claims: 1, 15-18, 20-22, 32, and 47

2. Patent Overview

• Title: VLSI Layouts of Fully Connected Generalized Networks
• Brief Description: The ’523 patent discloses layouts for Very-Large-Scale Integration (VLSI) multi-stage routing networks, such as those used in Field-Programmable Gate Arrays (FPGAs). The technology aims to create efficient and non-complex layouts by using a two-dimensional grid of sub-integrated circuit blocks with specific arrangements of horizontal and vertical cross-links between switches in successive stages.

3. Grounds for Unpatentability

Ground 1: Anticipation over Konda '756 PCT - Claims 1, 16, 20-22, and 32 are unpatentable under pre-AIA 35 U.S.C. §102(b) as anticipated by Konda '756 PCT.

• Prior Art Relied Upon: Konda (WO 2008/109756) (“Konda ’756 PCT”).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Konda ’756 PCT, by incorporating the ’394 provisional application, expressly discloses every limitation of the challenged claims. Independent claim 1 recites an integrated circuit with a plurality of sub-integrated circuit blocks and a routing network arranged in stages. Petitioner contended that Konda ’756 PCT’s Figure 1B shows a five-stage network (satisfying the y≥1 limitation), where each row of switches constitutes a sub-integrated circuit block. The reference allegedly discloses a plurality of 2x2 switches (d=2), forward and backward connecting links (right-going and left-going middle links), and straight and cross links as defined in the patent. For dependent claims, Petitioner asserted Konda ’756 PCT teaches the use of SRAM or Flash cells to program the switches (claim 16), the inclusion of configurable logic blocks or arbitrary digital circuits (claim 20), one-time programmable cross-points for ASICs (claim 21), passive cross-points (claim 22), and the specific connectivity of straight and cross links (claim 32).

Ground 2: Obviousness over Konda '756 PCT - Claims 15 and 17 are obvious over Konda '756 PCT.

• Prior Art Relied Upon: Konda ’756 PCT (WO 2008/109756).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground asserted that features in dependent claims 15 and 17 would have been obvious modifications of the device disclosed in Konda ’756 PCT. Claim 15 requires horizontal and vertical links to be implemented on two or more metal layers. Claim 17 requires the sub-integrated circuit blocks to be of equal die size.
  • Motivation to Combine (Modify): Petitioner argued a person of ordinary skill in the art (POSITA) would have been motivated to implement the links on multiple metal layers (claim 15), a standard practice in complex integrated circuits to manage routing and prevent shorts, a motivation supported by Konda ’756 PCT’s disclosure of using "vias" to connect links. For claim 17, a POSITA would have been motivated to use an identical layout (equal die size) for each sub-integrated circuit block to ensure manufacturing efficiency, design simplicity, and uniform operational characteristics (e.g., delays, drive strength), which is a predictable design choice.
  • Expectation of Success: Petitioner contended that implementing these known design principles—multi-layer metal routing and layout reuse—would have yielded predictable results, leading to a high expectation of success.

Ground 3: Obviousness over Konda '756 PCT in view of Wong - Claims 18 and 47 are obvious over Konda '756 PCT in view of Wong.

• Prior Art Relied Upon: Konda ’756 PCT (WO 2008/109756) and Wong (Patent 6,940,308).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addressed claim 18, which requires the sub-integrated circuit blocks to be Lookup Tables (LUTs) in an FPGA, and claim 47, which adds buffers to the connecting links. Petitioner asserted that while Konda ’756 PCT discloses an FPGA network, it does not explicitly name the logic blocks as LUTs or mention buffers. Wong, which is in the same field of FPGA interconnection networks, allegedly remedies these omissions by disclosing the use of LUTs as the logic cells connected by a routing network and the insertion of buffers on routing lines to manage signal delay and integrity.
  • Motivation to Combine: A POSITA implementing the Konda ’756 PCT network in an FPGA would have been motivated to consult a reference like Wong for standard implementation details. Wong teaches that logic cells in FPGAs can be LUTs and that buffers are a common solution for improving signal performance on long routing lines. Combining these known elements from Wong with the Konda ’756 PCT network architecture was argued to be a predictable combination of known components for their known purposes.
  • Expectation of Success: Petitioner argued a POSITA would have had a high expectation of success in combining the teachings, as it involved applying standard FPGA components (LUTs and buffers) to an interconnection network to achieve their well-understood functions.

4. Key Technical Contentions (Beyond Claim Construction)

• Priority Date Challenge: A central contention of the petition was that the ’523 patent is not entitled to its claimed priority date of May 25, 2007. Petitioner argued that the original claims required a "plurality of stages," but an amendment during prosecution broadened the claims to cover a network with only a single stage (y ≥ 1). Petitioner asserted that the priority applications fail to provide written description support for or enable a single-stage network that also possesses the claimed forward, backward, straight, and cross connecting links, as these links inherently require connections between different stages. By successfully challenging the priority date, Petitioner established that Konda ’756 PCT (published September 12, 2008) qualifies as prior art under pre-AIA §102(b) against the ’523 patent, whose effective filing date Petitioner argued is its national stage entry date of November 22, 2009.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 15-18, 20-22, 32, and 47 of the ’523 patent as unpatentable.