PTAB

IPR2020-00261

Flex Logix Technologies Inc v. Konda Venkat

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: VLSI Layouts of Fully Connected Generalized Networks
  • Brief Description: The ’523 patent discloses layouts for multi-stage hierarchical networks, such as those used in Field-Programmable Gate Arrays (FPGAs). The invention purports to provide efficient and non-complicated layouts by using horizontal and vertical cross links to connect switches between succeeding stages of the network.

3. Grounds for Unpatentability

Ground 1: Claims 2-7 are anticipated under pre-AIA 35 U.S.C. § 102(b) by Konda '756 PCT.

  • Prior Art Relied Upon: Konda '756 PCT (WO 2008/109756).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Konda '756 PCT, primarily through its incorporation by reference of U.S. Provisional Application No. 60/940,394, explicitly and inherently disclosed every limitation of claims 2-7. The argument is built upon an element-by-element mapping of base claim 1, which teaches an integrated circuit with a multi-stage routing network composed of sub-integrated circuit blocks arranged in a two-dimensional grid. Petitioner contended Konda '756 PCT disclosed the requisite pluralities of stages, switches, forward and backward connecting links (both straight and cross links), and connections to configurable logic blocks. For the challenged dependent claims, Petitioner asserted Konda '756 PCT disclosed: a network scalable by any power of two (claim 2); cross links connecting as alternating vertical and horizontal links (claim 3); the use of "shuffle exchange links" (claim 4); shuffle exchange links of substantially equal length (claim 5); and link lengths that double in each succeeding stage (claim 6). For claim 7, Petitioner argued Konda '756 PCT’s disclosed network met the claimed relationship between the number of stages and the size of the grid, and the required length of the links in the highest stage.

Ground 2: Claim 11 is obvious over Konda '756 PCT in view of Wong.

  • Prior Art Relied Upon: Konda '756 PCT (WO 2008/109756) and Wong (Patent 6,940,308).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Konda '756 PCT taught all limitations of the claims on which claim 11 depends (claims 1, 6, and 7), but did not explicitly disclose the final limitation of claim 11: "a plurality of U-turn links within switches in each of said stages." Petitioner asserted that Wong, which addresses interconnection networks for FPGAs, supplied this missing element. Wong taught a feature called "corner turning," which allowed signals to "turn the corner" within the network to create shorter routes between logic cells. Petitioner’s expert contended that a person of ordinary skill in the art (POSITA) would have understood Wong's "corner turning" to be functionally identical to the "U-turn links" recited in claim 11.
    • Motivation to Combine: A POSITA seeking to improve the performance of the network disclosed in Konda '756 PCT would have been motivated to consult prior art in the same field, such as Wong. Wong explicitly taught that its "corner turning" feature was "highly desirable for reducing the signal delay due to routing." Therefore, a POSITA would combine Wong's teachings with the Konda '756 PCT network to achieve a faster, more efficient circuit by providing shorter signal paths.
    • Expectation of Success: The proposed combination was argued to be a predictable application of known technologies. Wong provided clear teachings on how to implement corner turning in network switches. Integrating this known switch functionality into the established network architecture of Konda '756 PCT would have been a straightforward modification for a POSITA, with a high expectation of achieving the predictable result of a faster network.

4. Key Technical Contentions

  • Denial of Priority Date: A central contention of the petition was that the ’523 patent was not entitled to the filing date of its priority applications. Petitioner argued that during prosecution, the patent owner amended the claims to encompass a network where each sub-integrated circuit block could have only a single stage (y ≥ 1). Petitioner asserted that the priority applications lacked written description and enablement for a single-stage network that also contained the claimed "forward connecting links" and "backward connecting links," as those links by definition connect switches between different stages. By invalidating the priority claim, Petitioner argued the ’523 patent’s effective filing date was November 22, 2009, which rendered Konda '756 PCT (published September 12, 2008) available as prior art under §102(b).

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 2-7 and 11 of the ’523 patent as unpatentable.