PTAB

IPR2020-00374

Nuvoton Technology Corp v. Microchip Technology Inc

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1. Case Identification

2. Patent Overview

  • Title: Direct Memory Access Controller
  • Brief Description: The ’873 patent discloses direct memory access (DMA) controllers for transferring data between memory and peripheral devices without processor supervision. The technology centers on using transfer descriptors to define data transfers and priority-based arbitration schemes to manage multiple, concurrent transfer requests.

3. Grounds for Unpatentability

Ground 1: Obviousness over Kraus and Marenin - Claims 16, 20, and 23 are obvious over Kraus in view of Marenin.

  • Prior Art Relied Upon: Kraus (Application # 2007/0192515) and Marenin (Patent 5,195,185).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kraus, a DMA controller system not cited during prosecution, taught the core method steps of independent claim 16, including selecting an active DMA channel based on priority, receiving a transfer descriptor from memory, and performing the data transfer. The key distinction was that Kraus taught re-arbitrating among channels after the transfer of a data "burst," whereas claim 16 requires arbitrating after each "beat" of data.
    • Motivation to Combine (for §103 grounds): Petitioner asserted that Marenin taught a DMA arbitration scheme that occurs after each "beat" (defined by Petitioner as a clock cycle). A person of ordinary skill in the art (POSITA) would combine Marenin's beat-based arbitration with Kraus's system to improve performance. This modification would provide greater flexibility and improve Quality of Service (QoS) by reducing the latency inherent in waiting for a potentially long data burst to complete before re-evaluating channel priorities.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success, as Kraus already disclosed that its data burst size was "variable and programmable." Modifying the programmable burst length to be a single beat would have been a simple, predictable adjustment requiring minimal changes to the existing Kraus architecture.

Ground 2: Obviousness over Kraus, Marenin, and Trainin - Claims 1, 3-6, 11, 14, and 15 are obvious over Kraus in view of Marenin and Trainin.

  • Prior Art Relied Upon: Kraus (Application # 2007/0192515), Marenin (Patent 5,195,185), and Trainin (Patent 7,551,638).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targeted system claim 1, which largely mirrors method claim 16. Petitioner argued Kraus and Marenin combined to teach a DMA controller with a channel arbiter that arbitrates after each beat of data. The additional reference, Trainin, was introduced to teach limitations related to enabling and disabling DMA channels. Specifically, Trainin taught a DMA controller that fetches a transfer descriptor from a host memory and stores it in its own memory to enable a channel, and subsequently removes that descriptor to disable the channel after the transfer is complete (relevant to dependent claim 11).
    • Motivation to Combine (for §103 grounds): A POSITA would combine Trainin's fetching-and-storing mechanism to increase the operational readiness and efficiency of the core Kraus/Marenin system. Pre-fetching descriptors, as taught by Trainin, allows for the creation of a processing pipeline, increasing system throughput. Removing completed descriptors frees up memory resources and reduces the computational load on the arbiter.
    • Expectation of Success (for §103 grounds): Success was predictable because fetching data from a host memory was a well-known controller function. Since Kraus's controller already read descriptor lists from memory, modifying it to explicitly fetch and place them in a local buffer as taught by Trainin represented a straightforward and well-understood design choice.

Ground 3: Obviousness over Kraus, Marenin, and Garcia - Claim 22 is obvious over Kraus and Marenin in view of Garcia.

  • Prior Art Relied Upon: Kraus (Application # 2007/0192515), Marenin (Patent 5,195,185), and Garcia (Patent 5,448,702).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed dependent claim 22, which requires retrieving a second transfer descriptor using an address contained within the current transfer descriptor (i.e., "chained" descriptors). Petitioner argued that while the base Kraus/Marenin combination taught completing a transfer, it lacked this linking feature. Garcia was added to explicitly teach a DMA system using a "chain pointer" within a current descriptor block to point to the memory location of the next descriptor.
    • Motivation to Combine (for §103 grounds): A POSITA would incorporate Garcia’s descriptor chaining method into the Kraus/Marenin system to improve efficiency and system readiness. Chaining descriptors eliminates the timing delay associated with waiting for the arbiter to complete a full arbitration cycle, allowing the controller to immediately begin processing the next transfer in a predefined sequence.
    • Expectation of Success (for §1e03 grounds): There was a high expectation of success because Kraus's descriptor manager was already described as being capable of "looking ahead" at pending data transfer requests. Adding a "next address" field to the descriptor format, as taught by Garcia, would simply leverage this existing look-ahead capability and would have involved little more than expanding the descriptor's control/status field, a trivial modification for a POSITA.

4. Key Claim Construction Positions

  • Petitioner argued that the term "beat of data" should be narrowly construed to mean "a clock cycle." This construction was asserted to be required by the patent’s specification and, more importantly, by prosecution history estoppel. Petitioner contended that the patentee added the term "beat" to the claims during prosecution specifically to overcome prior art, thereby surrendering any broader interpretation.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review (IPR) and the cancellation of claims 1, 3-6, 11, 14-16, 20, 22, and 23 of Patent 9,442,873 as unpatentable under 35 U.S.C. §103.