PTAB

IPR2020-00394

Nuvoton Technology Corp v. Microchip Technology Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Sharing Non-Sharable Devices Between an Embedded Controller and a Processor in a Computer System
  • Brief Description: The ’576 patent discloses a method for sharing a non-volatile memory between a processor and a microcontroller without requiring a dedicated arbitration circuit. The patented method involves the microcontroller holding the main processor in a reset state upon system power-up, which grants the microcontroller exclusive access to the shared memory to load its own firmware before releasing the processor to boot.

3. Grounds for Unpatentability

Ground 1: Claims 17, 18, 20, 21, 188, 189, and 213 are obvious over Le.

  • Prior Art Relied Upon: Le (Patent 6,154,838).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Le, a reference applied during original prosecution, teaches or suggests every element of the challenged claims. Le discloses a microcontroller that, in response to a power-on reset, holds a processor's reset line active to gain exclusive ownership of a shared flash ROM. While the processor is held in reset, Le's microcontroller performs an integrity check (e.g., a checksum) of the ROM content before releasing the reset line. Petitioner contended that the examiner erred in finding Le did not teach loading data into the microcontroller's memory. A person of ordinary skill in the art (POSITA) would have understood that the disclosed 8051 microcontroller must fetch data from the external ROM and load it into its internal memory (RAM or registers) to perform the checksum, thereby satisfying the key "fetching and loading" limitation of independent claim 17. The dependent claims were argued to be obvious for reciting conventional features also taught by Le, such as using the microcontroller as a keyboard controller.

Ground 2: Claims 17, 18, 20, 21, 188, 189, and 213 are obvious over Le in view of Wang.

  • Prior Art Relied Upon: Le (Patent 6,154,838) and Wang (Application # 2004/0049727).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative invalidity theory. Petitioner argued Le discloses the core method of controlling processor access to a shared memory via a reset signal (claim limitations [1] and [3]). Wang was cited to explicitly teach the "fetching and loading" limitation (claim limitation [2]), as Wang describes a microprocessor fetching the contents of an external flash ROM and loading them into its internal RAM to perform a checksum computation.
    • Motivation to Combine: A POSITA would combine the references to improve Le's system. Because Le’s method calls for a memory integrity check, a POSITA would have looked to known techniques for performing such a check, like the checksum method explicitly detailed in Wang. The combination involved applying a known technique to a known system to achieve a predictable result.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the 8051 microcontroller disclosed in Le was fully capable of performing the conventional checksum process taught by Wang.

Ground 3: Claims 17, 18, 20, 21, 188, 189, and 213 are obvious over Le in view of Triece.

  • Prior Art Relied Upon: Le (Patent 6,154,838) and Triece (Application # 2003/0056071).
  • Core Argument for this Ground:
    • Prior Art Mapping: Similar to Ground 2, this ground relied on Le for the processor reset control framework. Triece was offered as an alternative reference to explicitly teach the "fetching and loading" limitation. Triece discloses a conventional method for booting a microcontroller by fetching and loading a program from an external program memory into the microcontroller's internal boot memory.
    • Motivation to Combine: A POSITA would have been motivated to implement the booting process of Triece within the system of Le. Le’s microcontroller must boot up while the processor is held in reset, and Triece provides a known, conventional method for accomplishing this. Implementing Triece's method would have been a simple design choice that could also reduce overall system cost by removing the need for onboard ROM in Le's microcontroller.
    • Expectation of Success: Success would have been predictable, as booting a microcontroller by loading a program from external memory was a well-known and conventional technique.
  • Additional Grounds: Petitioner asserted additional obviousness challenges specifically for claim 213 based on combinations of Le with Lin, and Le with Wang/Triece and Lin, arguing Lin provided further teachings on the architecture for communicating reset signals between a keyboard controller (microcontroller) and a processor via a system interface.

4. Key Technical Contentions (Beyond Claim Construction)

  • A central technical contention, particularly for Ground 1, was that the original patent examiner misunderstood the inherent operation of the 8051 microcontroller disclosed in Le. Petitioner argued that a POSITA would have known that for an 8051 microcontroller to perform operations like a checksum on data from an external memory, it must first fetch that data and load it into its internal memory (e.g., RAM or registers), thereby satisfying the key "loading" limitation of the challenged claims without needing an explicit teaching.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 17, 18, 20, 21, 188, 189, and 213 of the ’576 patent as unpatentable.