Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00527
• Patent #: 6,633,187
• Filed: February 13, 2020
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 14-16, 19, and 20

2. Patent Overview

• Title: Power-On-Reset for Integrated Circuits with On-Chip Power Converters
• Brief Description: The ’187 patent discloses a power-on-reset (POR) technique for a stand-alone integrated circuit (IC) containing an on-chip power converter. The invention claims a specific sequence where the IC is held in an idle reset state until the on-chip converter generates a stable supply voltage, at which point the IC's functionality is enabled.

3. Grounds for Unpatentability

Ground I: Obviousness over Page, Yamamoto, and LeWalter - Claims 15, 16, and 19 are obvious over Page in view of Yamamoto and LeWalter.

• Prior Art Relied Upon: Page (Patent 6,980,037), Yamamoto (Patent 5,778,237), and LeWalter (Patent 5,739,708).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Page teaches the foundational stand-alone IC with an on-chip power converter and a POR circuit that holds clocks until voltage is stable. Because Page suggests a software implementation without detailing the required processing module and memory, Petitioner asserted that Yamamoto supplies this missing element by teaching a single-chip microcomputer with a processor and memory to execute instructions for POR functionality. For claim 15's requirement of "enabling a reset signal," Petitioner asserted that LeWalter provides specific implementation details that Page lacks, teaching a specific RES signal to hold a circuit in an idle reset condition until a clock signal stabilizes.
  • Motivation to Combine: A POSITA would combine Page with Yamamoto to implement Page's POR functions in software on a single chip, a known method to reduce size, cost, and power consumption. A POSITA would also incorporate LeWalter's reset signal into Page’s system to provide a concrete, known implementation for the idle state that Page described conceptually, as both references concern POR techniques for ICs.
  • Expectation of Success: Petitioner contended that combining a standard processor/memory (Yamamoto) and a known reset signal implementation (LeWalter) with Page's POR circuit was a predictable integration of known elements to achieve the desired software-controlled reset functionality.

Ground II: Obviousness over Page, Yamamoto, LeWalter, and Yasuda - Claim 20 is obvious over Page in view of Yamamoto, LeWalter, and Yasuda.

• Prior Art Relied Upon: Page (Patent 6,980,037), Yamamoto (Patent 5,778,237), LeWalter (Patent 5,739,708), and Yasuda (Patent 5,936,443).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on the combination for claim 19, adding the limitation of de-asserting the reset signal upon detection of both a "clock lock signal" and a "supply lock signal." Petitioner argued LeWalter teaches generating and detecting a "clock lock signal" to confirm clock stability before operation. For the "supply lock signal," Petitioner asserted Page's TMI_RSTZ signal meets the limitation because it signals that the converter's output voltage is stable. Alternatively, Yasuda was cited for its explicit teaching of a POR circuit that generates a signal only after an internal voltage supply has stabilized, serving as a clear supply lock signal.
  • Motivation to Combine: A POSITA would be motivated to require both clock stability (from LeWalter) and supply voltage stability (from Page or Yasuda) before enabling the IC's operation. This combination would enhance overall system reliability, a primary goal of POR circuits.
  • Expectation of Success: Implementing checks for both stable voltage and a stable clock were known reliability measures. Petitioner argued combining these known techniques from the references was a predictable design choice to create a more robust POR system.

Ground III: Obviousness over Page, Yamamoto, and Goder - Claim 14 is obvious over Page in view of Yamamoto and Goder.

• Prior Art Relied Upon: Page (Patent 6,980,037), Yamamoto (Patent 5,778,237), and Goder (Patent 5,617,015).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses the limitation of the on-chip converter generating two distinct supplies from a single inductor. Petitioner argued that Page's base system, with its single-output on-chip converter, would have been modified by a POSITA with the teachings of Goder. Goder was cited for explicitly disclosing a switching voltage regulator that provides multiple, independently regulated voltage outputs from a single inductor.
  • Motivation to Combine: A POSITA would combine these references to meet the increasing industry demand for ICs with multiple voltage domains to save power, a concept known as Dynamic Voltage and Frequency Scaling. Modifying Page's single-supply converter with Goder's multiple-supply, single-inductor design was a known way to provide different voltages to different parts of the IC, thereby increasing power efficiency.
  • Expectation of Success: Goder's single-inductor, multiple-output converter technology was well-known and could be predictably integrated into Page's IC design, especially since Goder itself suggests implementation in an integrated circuit.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) and §325(d). The petition asserted it was filed in response to the Patent Owner's belated assertion of new claims in a parallel district court case and that there was no overlap in challenged claims or grounds with prior IPRs. Petitioner contended that the complex, multi-reference obviousness grounds are better suited for the PTAB's technical expertise than for a jury, and that the uncertain trial schedule in the co-pending litigation makes an IPR a more efficient forum for resolving validity.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 14-16, 19, and 20 of the ’187 patent as unpatentable.