PTAB

IPR2020-00539

Intel Corp v. PACT XPP Schweiz AG

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1. Case Identification

2. Patent Overview

  • Title: Multiprocessor System with Runtime-Adjustable Clock and Voltage
  • Brief Description: The ’047 patent discloses a multiprocessor system comprising a plurality of data processing units (DPUs). The system is designed to manage power consumption by selectively adjusting the clock frequency and supply voltage of individual DPUs at runtime based on various parameters like system state or temperature.

3. Grounds for Unpatentability

Ground I: Claims 1-7, 17-20, 22, 23, 27, and 33 are obvious over Nicol.

  • Prior Art Relied Upon: Nicol (Patent 6,141,762).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Nicol discloses every element of the independent claims. Nicol teaches a multiprocessor system with multiple processing elements (PEs) where a controller dynamically allocates tasks and adjusts the clock frequency and supply voltage for each PE at runtime to minimize power consumption. This includes supplying higher voltages for higher clock frequencies. Petitioner asserted that Nicol's PEs are programmable, include an ALU and registers, are interconnected by a bus system, and are adaptable for sequential data processing, as a person of ordinary skill in the art (POSITA) would understand that systems for digital signal processing applications, like Nicol's, commonly use pipelined or systolic architectures where results from one PE are passed to another.
    • Key Aspects: This ground asserted that Nicol alone renders the core invention obvious, as its central teaching is dynamic voltage and frequency scaling in a multiprocessor system, which is the crux of the ’047 patent.

Ground II: Claims 8-16, 21, 24, 28, and 30 are obvious over Nicol in combination with Bhatia.

  • Prior Art Relied Upon: Nicol (Patent 6,141,762), Bhatia (Patent 6,535,798).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claims requiring features like heterogeneous processors and thermal management. Petitioner argued Nicol provides the base multiprocessor system with dynamic power control. Bhatia was introduced for its teachings on thermal management in a heterogeneous system (having processors of different types), including using multiple dispersed temperature sensors to monitor different thermal zones. Bhatia explicitly taught dynamically adjusting clock frequency in response to sensed over-temperature conditions by switching between performance states. It also taught low-power states (e.g., C3 state) where inactive processors are deactivated to save power while preserving memory contents.
    • Motivation to Combine: A POSITA would combine the references because both address the interrelated and critical fields of power and thermal management in processor systems. A POSITA seeking to improve Nicol's power-focused system would have been motivated to incorporate Bhatia's well-known over-temperature protection and thermal monitoring techniques, which is a critical feature for high-performance systems.
    • Expectation of Success: The combination would have yielded predictable results, as it involved adding well-understood, software-based thermal management and low-power state functionalities (per the ACPI standard cited in Bhatia) to Nicol's flexible and extensible multiprocessor architecture.

Ground III: Claims 1-7, 17-20, 22, 23, 27, and 33 are obvious over Nicol in combination with DeHon.

  • Prior Art Relied Upon: Nicol (Patent 6,141,762), DeHon (Patent 6,052,773).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground was argued under Petitioner's proposed claim construction, which required the DPUs to be "reconfigurable." Petitioner asserted that while Nicol taught the base multiprocessor system, DeHon taught reconfigurable microprocessor chips that include a programmable gate array. DeHon explained that its reconfigurable processors could be used as the primary building block in a wide range of applications, including multiprocessor systems, and could be configured to handle various compute-intensive functions where data is passed between functional units.
    • Motivation to Combine: Nicol itself provided the motivation, as it described its system as being intended for a "mix of many digital signal processing applications." A POSITA would have been motivated to implement DeHon's flexible, reconfigurable processors as the PEs in Nicol's system to better handle this changing mix of applications through rapid, application-specific reconfiguration.
    • Expectation of Success: A POSITA would have had a high expectation of success because Nicol's power management scheme was described as "extendible to other system arrangements" and thus agnostic to the specific type of PE (fixed or reconfigurable).

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground IV) against claims 8-16, 21, 24, 28, and 30 based on the combination of Nicol, Bhatia, and DeHon under its proposed claim construction.

4. Key Claim Construction Positions

  • A central issue in the petition was the construction of the claim term "data processing unit . . . adaptable for sequentially processing data" and its variants. The petition advanced arguments for invalidity under two alternative constructions.
    • Patent Owner's Proposed Construction: "passing results onto one or more other data processing units which are subsequently processing data." Petitioner argued the claims were obvious even under this construction (Grounds I and II).
    • Petitioner's Proposed Construction: "reconfigurable and sequential data processors where the data results from one processor are fed to another, for each processor to perform a separate computation." This construction was based on the patent's specification emphasizing "reconfigurable architecture" and was used to support the grounds including DeHon (Grounds III and IV).

5. Key Technical Contentions (Beyond Claim Construction)

  • Applicability of Systolic Architectures: A key contention, particularly for Ground I, was that a POSITA would have understood that the PEs in Nicol's system could be configured to sequentially process data in a manner similar to a well-known systolic architecture. Petitioner argued that because Nicol was designed to handle a "mix of many digital signal processing applications," it would have been obvious to arrange the PEs to perform operations in a pipeline fashion, where data flows from one PE to the next for subsequent processing. This was used to argue that Nicol inherently taught the "sequentially processing data" limitation without needing a secondary reference.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-24, 27, 28, 30, and 33 of the ’047 patent as unpatentable.