PTAB

IPR2020-00540

Intel Corp v. PACT XPP Schweiz AG

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Reconfigurable Multiprocessor System-on-Chip
  • Brief Description: The ’807 patent describes systems with a plurality of processing elements (each including an ALU and registers), memory elements that operate as caches, and interface elements for connecting to high-level memory. These components are interconnected by a reconfigurable bus system for transferring data.

3. Grounds for Unpatentability

Ground 1: Claims 3-4, 9, 24, 26, 27, 30, 42, 73, and 74 are obvious over Barroso and the Alpha Manual.

  • Prior Art Relied Upon: Barroso ("Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing," pub. 2000) and the Alpha Manual ("Alpha AXP Architecture Reference Manual," pub. 1995).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of Barroso and the Alpha Manual teaches all limitations of the challenged claims. Barroso discloses a system-on-a-chip ("Piranha") with multiple Alpha CPU cores, L1 and L2 caches, memory controllers, and an intra-chip switch (ICS) that functions as the claimed bus system. The Alpha Manual, which Barroso explicitly references, describes the detailed architecture of the Alpha CPU cores, teaching the required arithmetic-logic unit (ALU) and plurality of registers for storing data. Barroso further discloses an "identification token" (its "transaction address") assigned to transmitted data to affiliate it with a specific process (an executing thread), satisfying a key limitation of claims 3 and 4.
    • Motivation to Combine: A POSITA would combine the teachings because Barroso expressly uses and cites the Alpha Manual to describe its Alpha processor cores. A POSITA seeking to understand the full functionality of Barroso's processor cores would have naturally consulted the Alpha Manual to supplement Barroso's disclosure, such as by incorporating the plurality of registers described therein to improve performance and reduce latency.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success, as Barroso's system is already based on the Alpha processor architecture. Integrating the detailed register structures from the Alpha Manual into Barroso's Alpha cores would be a straightforward implementation yielding the predictable result of a fully functional processor core.

Ground 2: Claims 1, 5, 32, and 44 are obvious over Barroso and the Alpha Manual in view of Nickolls or, alternatively, Godfrey.

  • Prior Art Relied Upon: Barroso, the Alpha Manual, Nickolls (Patent 5,598,408), and Godfrey (Patent 6,266,797).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addresses independent claim 1, which requires the bus system to be adapted for forming at least one ring via interconnection elements that include "pipeline-registers." Petitioner asserted that Barroso's system, when multiple Piranha chips are connected, forms a ring-shaped network. Nickolls teaches improving such interconnection systems by adding pipeline registers at the junctures of routing path segments to substantially increase messaging speed. Alternatively, Godfrey discloses a reconfigurable circular bus system that forms communication rings. Combining Godfrey's bus with Nickolls' pipeline registers would satisfy the claim limitation. Claim 32 adds the requirement for "simultaneously transferring data," which Godfrey's concurrent communication paths and Barroso's multiple datapaths both teach.
    • Motivation to Combine: A POSITA would combine Nickolls with Barroso to improve the performance of Barroso’s interconnection system, a known design goal. Alternatively, a POSITA would replace Barroso’s less flexible ICS with Godfrey’s superior circular bus architecture to improve routing and concurrency. Adding Nickolls’ pipeline registers to Godfrey’s communication ports would be a known method to maximize data flow rates.
    • Expectation of Success: Adding pipeline registers was a well-known technique for improving interconnection systems. A POSITA would have reasonably expected that incorporating them into the ring networks of Barroso or the bus system of Godfrey would predictably increase data throughput without undue experimentation.

Ground 3: Claims 2, 6, and 29 are obvious over Barroso, the Alpha Manual, Godfrey, and Nickolls.

  • Prior Art Relied Upon: Barroso, the Alpha Manual, Godfrey, and Nickolls.
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds on the combination of Ground 2, adding limitations from dependent claims 2, 6, and 29. The key additional limitation is that the ring is adapted for transmitting data in at least two directions using "separate and independent structures" for each direction. Petitioner argued that Godfrey explicitly discloses this feature. Godfrey's system uses separate, bi-directionally coupled communication ports with independent MUX/DEMUX structures that are configured to transmit data in opposite directions along its circular bus, satisfying the limitation.
    • Motivation to Combine: The motivation to combine the references is the same as in Ground 2: to improve the routing performance, flexibility, and concurrency of the base Barroso multiprocessor system by incorporating Godfrey's advanced, reconfigurable ring bus architecture and Nickolls' performance-enhancing pipeline registers.
    • Expectation of Success: As the individual components were known in the art for their specific functions, a POSITA would have a reasonable expectation that combining them would result in a system possessing the aggregated, predictable functionalities of each reference.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-6, 9, 24, 26, 27, 29, 30, 32, 42, 44, 73, and 74 as unpatentable.