NVIDIA Corp v. Tessera Advanced Technologies Inc

1. Case Identification

• Case #: IPR2020-00581
• Patent #: 5,666,046
• Filed: February 14, 2020
• Petitioner(s): NVIDIA Corporation
• Patent Owner(s): Tessera Advanced Technologies, Inc.
• Challenged Claims: 20-22

2. Patent Overview

• Title: Method for Generating a Bandgap Output Reference Voltage
• Brief Description: The ’046 patent discloses a method and circuit for generating a temperature-stable reference voltage, commonly known as a bandgap reference circuit. The disclosed invention generates a first current with a positive temperature coefficient and a second current with a negative temperature coefficient, sums them to create a temperature-independent output current, and then generates the final reference voltage from this output current.

3. Grounds for Unpatentability

Ground 1: Claims 20-22 are obvious over Hara in view of the knowledge of a POSITA.

• Prior Art Relied Upon: Hara (Japanese Patent Application No. H5-251954).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Hara discloses a current-summing bandgap reference circuit that teaches every limitation of the challenged claims and is virtually identical in topology and operation to the preferred embodiment of the ’046 patent.
    • Independent Claim 20: Petitioner asserted that Hara’s circuit performs the claimed method for generating an output voltage with a substantially zero temperature coefficient. Specifically, Hara generates a first current with a positive temperature coefficient from the voltage difference (ΔVBE) across a set of p-n junctions in two bipolar transistors (Tr11, Tr12) operating at different current densities. Hara then generates a second current with a negative temperature coefficient from the base-emitter voltage (VBE) of one of those transistors (Tr11). These two currents, one positive-TC and one negative-TC, are then summed at a common node, and the resulting temperature-independent output current is passed through a resistor (R13) to generate the final, stable output voltage (Vref).
    • Dependent Claim 21: Petitioner contended that Hara discloses setting the output voltage level independently of the temperature coefficient. Hara’s equations allegedly show that the value of resistor R13 determines the final voltage level, while other parameters (e.g., transistor scaling factors M and N, resistor values R11 and R12) independently determine the temperature coefficient of the summed currents.
    • Dependent Claim 22: Petitioner argued that Hara explicitly teaches operating two bipolar transistors (Tr11 and Tr12) at different current densities to generate the ΔVBE voltage required for the positive-TC current, meeting this limitation.
  • Motivation to Combine (for §103 grounds): Petitioner asserted that Hara itself provides the motivation to combine the circuit elements as claimed. Hara’s explicit purpose was to create a temperature-stable reference voltage by generating and summing currents with opposing temperature coefficients. The reliance on POSITA knowledge was primarily to establish that minor differences, such as Hara’s use of NPN transistors versus the ’046 patent’s preferred use of PNP transistors, represented a simple and well-known design choice based on available manufacturing processes.
  • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because Hara’s circuit employs conventional components (op-amps, transistors, resistors) operating according to fundamental and predictable principles of circuit design, such as Ohm’s law and Kirchhoff’s current law.

4. Key Claim Construction Positions

• Petitioner argued that no express claim construction was necessary to resolve the challenge. However, Petitioner addressed the term "set of p-n junctions" from claim 20, which was a point of contention in a prior IPR (IPR2017-00810) involving the ’046 patent. Petitioner asserted that Hara’s bipolar transistors Tr11 and Tr12 comprise at least “two p-n junctions” or a “plurality of p-n junctions,” and therefore Hara’s disclosure meets the limitation under either construction previously proposed by the parties in the prior IPR.

5. Key Technical Contentions (Beyond Claim Construction)

• A central technical contention was that the difference in transistor types between Hara (NPN bipolar transistors and n-channel MOSFETs) and the ’046 patent’s preferred embodiment (PNP bipolar transistors and p-channel MOSFETs) is an obvious and routine design choice. Petitioner argued that a POSITA would readily understand how to implement Hara’s circuit topology using complementary transistor types to suit a different CMOS manufacturing process (e.g., an n-well process requiring PNP transistors). The ’046 patent specification itself acknowledges that its transistors could be NPN types, supporting the argument that this is not a patentable distinction.

6. Arguments Regarding Discretionary Denial

• Petitioner presented extensive arguments that discretionary denial under 35 U.S.C. § 325(d) and the General Plastic factors would be inappropriate, despite a previously denied IPR petition against the ’046 patent. The core arguments were:
  • This petition was filed by a different petitioner (NVIDIA), which was not similarly situated to the prior petitioner (Broadcom).
  • The petition is based on a new primary prior art reference, Hara, which was not considered in the prior IPR or during the original prosecution of the ’046 patent.
  • The substantive obviousness rationale, grounded in Hara’s nearly identical circuit topology, had not been previously presented to or considered by the Patent Office or the Board.
  • The current petition was a direct result of the Patent Owner’s litigation activity against NVIDIA, which commenced after the prior IPR was resolved.

7. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 20-22 of the ’046 patent as unpatentable.