PTAB

IPR2020-00602

NVIDIA Corp v. Invensas Corp

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Substantially Planarized Interconnect Topography
  • Brief Description: The ’946 patent describes a semiconductor topography and fabrication method intended to improve surface planarity during chemical-mechanical polishing (CMP). The invention involves adding electrically isolated "dummy conductors" of specific dimensions into open dielectric areas between wider functional interconnects (e.g., bond pads) and narrower functional interconnects (e.g., signal lines) to create a more uniform pattern density, thereby reducing defects like dishing and erosion.

3. Grounds for Unpatentability

Ground 1: Obviousness over Jaso and Stine1998 - Claims 16-22 are obvious over Jaso in view of Stine1998.

  • Prior Art Relied Upon: Jaso (Patent 6,093,631) and Stine1998 (an IEEE journal article from March 1998).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Jaso disclosed the core method of the ’946 patent: adding "dummy circuitry" into open areas of an interconnect layer using a damascene process to create a more uniform pattern density and improve planarity after CMP. Jaso taught using dummy conductors of an "uncritical size" (e.g., 1 micron), which is wider than the minimum feature size ("critical dimension") of the time but narrower than large features like bond pads, thus meeting the intermediate-width limitation of claim 16. Petitioner asserted that Stine1998 complemented Jaso by providing a detailed case study of an actual integrated circuit layout, which explicitly identified the "large open areas" between wide peripheral interconnects (bond pads) and densely packed narrow core interconnects as "prime candidates" for adding dummy metal-fill to improve planarity. Stine1998’s scaled figures showed bond pads of ~200 microns and narrow interconnects of 3 microns, teaching the exact layout configuration recited in the claims.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Jaso and Stine1998 because both addressed the identical problem of pattern-dependent planarity issues in CMP by adding dummy features. Jaso provided the general damascene method, while Stine1998 provided a detailed, practical analysis of where to apply this method in a typical circuit layout and, critically, how to optimize the dummy feature geometry to balance the tradeoff between improved planarity and unwanted parasitic capacitance—an issue Jaso acknowledged but did not solve. Stine1998 expressly stated its methodology was extendable to damascene processes like Jaso’s.
    • Expectation of Success: A POSITA would have had a high expectation of success. Combining Stine1998's teachings on applying optimized dummy fill to the large open areas between wide and narrow interconnects with Jaso's damascene fabrication process was a straightforward application of known principles to achieve the predictable result of improved planarity with minimized electrical side effects.

Ground 2: Obviousness over Jaso, Stine1998, and Pramanik1998 - Claims 16-22 are obvious over Jaso and Stine1998 in further view of Pramanik1998.

  • Prior Art Relied Upon: Jaso (Patent 6,093,631), Stine1998 (an IEEE journal article), and Pramanik1998 (a conference proceeding paper from May 1998).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground reinforced the arguments from Ground 1, with Pramanik1998 providing additional, explicit evidence for the obviousness of applying the claimed solution. Petitioner argued that Pramanik1998, like the ’946 patent, specifically addressed CMP for copper-based damascene interconnects. It explicitly described the problem of "erosion for narrow and dense metal lines and dishing on wide metal lines" and taught the solution of "using dummy metal segments to fill open areas" to achieve a uniform pattern density. Its figures illustrated a cross-section with wide and narrow trenches separated by an open oxide area, which is virtually identical to a figure in the ’946 patent.
    • Motivation to Combine: A POSITA would combine Pramanik1998 with Jaso and Stine1998 because it provided a direct and explicit confirmation of the specific problem and solution within the context of copper damascene technology. While Jaso and Stine1998 provided the method and layout, Pramanik1998 expressly linked the specific defects (dishing, erosion) to the specific features (wide lines, narrow lines) and prescribed the specific solution (adding dummy features in open areas). This removed any doubt that a POSITA would apply the techniques of Jaso and Stine1998 to the claimed configuration.
    • Expectation of Success: The teachings of all three references were highly complementary and focused on the same problem, process, and solution. Combining them would predictably result in a damascene process with improved planarity by adding dummy conductors between wide and narrow interconnects.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under 35 U.S.C. §314(a) or §325(d) was improper because this petition presented new, stronger grounds for unpatentability than those considered in two prior inter partes review (IPR) proceedings (IPR2017-00107 and IPR2018-01402). The prior art references Stine1998 and Pramanik1998 were not asserted in the prior IPRs and were not before the examiner during original prosecution.
  • Petitioner further contended it was not the same party or "similarly situated" to the petitioners in the prior IPRs (Broadcom and Samsung), as NVIDIA was a defendant in a different district court litigation involving different accused products. Finally, Petitioner asserted that the filing of multiple petitions was a direct result of the Patent Owner’s serial litigation strategy, and that denying institution would be highly prejudicial to NVIDIA.

5. Relief Requested

  • Petitioner requested institution of IPR and cancellation of claims 16-22 of the ’946 patent as unpatentable.