PTAB

IPR2020-00726

Sony Interactive Entertainment Inc v. Bot M8 LLC

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1. Case Identification

2. Patent Overview

  • Title: Information Processing Device Fault Inspection
  • Brief Description: The ’670 patent discloses an information processing device, such as a gaming machine, designed to ensure system integrity. It describes storing a fault inspection program in a first memory device (e.g., ROM) on a motherboard, which is independent from a second memory device (e.g., hard disk) that stores game applications, to guarantee the inspection program itself is not compromised when it checks for faults.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sugiyama and Gatto - Claims 1-4 are obvious over Sugiyama in view of Gatto.

  • Prior Art Relied Upon: Sugiyama (Japanese Application JP 2000-35888) and Gatto (WO 2004/004855).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sugiyama taught the core architecture of the invention: a communication terminal (a karaoke machine) with a CPU, a first memory (ROM), and a second memory (HDD). Sugiyama’s ROM stores an HDD inspection program that executes to check for faults on the HDD before the main karaoke application is loaded. Petitioner contended this system met most limitations of independent claim 1. Gatto was cited to supply the explicit context of a "gaming device" and the common use of a motherboard, which Sugiyama did not expressly state but was inherent to its described structure. The combination thereby rendered claims 1-4 obvious.
    • Motivation to Combine: A POSITA would combine Sugiyama's fault-inspection architecture with Gatto's gaming device environment to improve the reliability and security of gaming terminals. Because both references address networked devices that download software and require integrity verification, Petitioner argued that applying Sugiyama’s secure inspection method to Gatto’s gaming context was a simple and predictable substitution of one application (karaoke) for another (gaming) to achieve a known goal.
    • Expectation of Success: Petitioner asserted a high expectation of success, as the combination involved applying well-understood computer architecture principles (secure boot inspection) to a known field (gaming machines) to solve a known problem (software integrity).

Ground 2: Obviousness over Sugiyama, Gatto, and Yamaguchi - Claim 5 is obvious over Sugiyama in view of Gatto and Yamaguchi.

  • Prior Art Relied Upon: Sugiyama (Japanese Application JP 2000-35888), Gatto (WO 2004/004855), and Yamaguchi (Patent 5,844,776).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 to address the additional limitation of claim 5, which requires a "connector" on the motherboard for connecting the second memory device. While the Sugiyama/Gatto combination taught the functional system, Petitioner introduced Yamaguchi to explicitly disclose the physical means of connection. Yamaguchi taught connecting a memory device like a hard disk drive to a motherboard using standard components, including a flat cable and connectors.
    • Motivation to Combine: A POSITA implementing the system of Sugiyama and Gatto would require a method to physically connect the hard drive to the motherboard. Petitioner argued that looking to a reference like Yamaguchi for a standard, well-known connection method would have been an obvious and necessary design choice to make the combined system operable.
    • Expectation of Success: The expectation of success was argued to be very high, as using connectors to attach peripherals like hard drives to motherboards was a ubiquitous and predictable practice in computer design at the time of the invention.

Ground 3: Obviousness over Morrow and Morrow ’771 - Claims 1-4 are obvious over Morrow in view of Morrow ’771.

  • Prior Art Relied Upon: Morrow (Application # 2004/0054952) and Morrow ’771 (Application # 2003/0064771).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner presented Morrow as an alternative primary reference that directly taught a gaming device with a verification software program (fault inspection program) stored in a first memory device (a BIOS chip). This program is executed by a CPU to verify components, including a second memory device (persistent storage media where games are stored), before any game program is run. The related Morrow ’771 reference, by the same inventor, was used to explicitly teach that the BIOS chip is located on a motherboard, thereby satisfying all limitations of claims 1-4.
    • Motivation to Combine: A POSITA would have been motivated to consult the related Morrow ’771 application to fully understand the hardware implementation of the system described in Morrow. This is because both documents share an inventor and describe similar Bally Gaming Systems technology, making it natural to combine their teachings to arrive at the claimed configuration.
    • Expectation of Success: Petitioner argued for a high expectation of success because the combination involved integrating information from two closely related patent applications to implement a common and predictable computer architecture for a gaming machine.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-5 of the ’670 patent as unpatentable.