PTAB

IPR2020-00908

Nichia Corp v. Document Security Systems Inc

Key Events

Petition

petition

Title: Surface Mountable Electronic Device
Brief Description: The ’040 patent relates to surface mount technology (SMT) for light-emitting diode (LED) devices. The invention is directed to a package structure with recesses at its side edges and electrical contacts that terminate within these recesses, allegedly improving solder bond strength and display resolution compared to prior art devices where conductive members extended beyond the package body.

Prior Art Relied Upon: Kim (Japanese Unexamined Patent Application Publication No. 10-200038).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Kim, which discloses a “bottom-lead semiconductor package” (BLP) designed to improve solder joint reliability, teaches every limitation of the challenged claims. Kim’s BLP allegedly includes a “packaged body” (molded resin body 37) with a “mounting surface” having recesses at its side edges (grooves 38 formed under internal leads 32). The electrical contacts (leads 33) extend from an interior portion of the mounting surface, terminate in, and conform to these recesses. Petitioner asserted that Kim’s structure is sized to provide the claimed “offsets” between the mounting surface and the electrical contacts. The arguments for dependent claims 2, 3, and 11 followed from this mapping, with Petitioner identifying portions of Kim's contacts that are parallel (claim 2) and not parallel (claim 3) to the mounting surface, and arguing the recesses are bounded on three sides (claim 11).

Prior Art Relied Upon: Kim (as in Ground 1) and Shirahata (Japanese Examined Patent Publication No. 7-50754B2).
Core Argument for this Ground:
- Prior Art Mapping: This ground targets claim 8, which requires the device to be an opto-electric or light-emitting device. Petitioner contended that while Kim discloses a general-purpose semiconductor package, it does not expressly disclose its use for an opto-electric component. Shirahata discloses a conventional prior art light-receiving semiconductor device packaged in a small outline package (SOP), the very type of package Kim was designed to improve upon.
- Motivation to Combine: A person of ordinary skill in the art (POSA) would combine Shirahata’s light-receiving semiconductor chip with Kim’s improved BLP package to achieve known benefits. Specifically, a POSITA would be motivated to gain the advantages taught by Kim—reduced package size, improved solder joint reliability, and reduced potential for damage to exposed leads—for the opto-electric device taught by Shirahata.
- Expectation of Success: A POSA would have had a reasonable expectation of success because Kim’s package was described for general semiconductor chips, and incorporating an opto-electric chip would have been a predictable implementation. Furthermore, the use of transparent resin for the package body, as would be needed for a light-emitting device, was a well-known and common practice.

Prior Art Relied Upon: Adachi (Japanese Unexamined Patent Application Publication No. 6-350206).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Adachi, which discloses a “chip-type light emitting electronic component,” anticipates all limitations of claims 1-4 and 8. Adachi’s device allegedly has a “packaged body” (comprising primary molding 1 and secondary molding 5) with a mounting surface containing a plurality of recesses at its side edges (identified as “cutaway portions 7”). The electrical contacts (lead electrode parts 3b and terminal parts 3e) are shown to extend from an interior portion, terminate in, and conform to these recesses. The structure is sized to create the claimed offsets. Because Adachi’s device contains an LED element, it inherently meets the limitation of claim 8. The parallel, non-parallel, and orthogonal portions required by dependent claims 2-4 were also allegedly disclosed.
Additional Grounds: Petitioner asserted additional anticipation challenges under §102 against claims 1-4 and 8 over Nagayama (Japanese Unexamined Patent Application No. 2000-77725) and against claims 1-4, 8, and 11 over Okazaki (Japanese Unexamined Patent Application No. 6-90026).

“mounting surface”: Petitioner argued this term should be construed as “a planar surface at which the device is mounted, which surface is essentially co-planar with the planar bottom surface of the body, and which surface does not follow the contours of its recesses.” This construction is central to resolving a perceived impossibility in the claims, where contacts must both “conform to” recesses in the mounting surface and be “offset” from that same surface.
“packaged body” / “body”: Proposed as “a protective shell to hold a semiconductor and electrical contacts.” This construction distinguishes the body from the electrical contacts it houses.
“conforms to”: Proposed as “is adapted to and follows the shape of.”
“offset”: Proposed as “space.”

Petitioner argued against discretionary denial under Fintiv by highlighting the early stage of a co-pending district court case, Document Security Systems, Inc. v. Nichia Corporation, No. 2:19-cv-08172 (C.D. Cal.). Petitioner stated that discovery had just begun, no significant deadlines had passed (including claim construction), and trial was set for approximately one and a half years in the future, suggesting an IPR would conclude long before trial.

Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-4, 8, and 11 of the ’040 patent as unpatentable.