PTAB

IPR2020-00985

Advanced Micro Devices Inc v. Monterey Research LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Circuit with Non-Interruptible Burst Addressing
  • Brief Description: The ’134 patent discloses a system and method for addressing a memory circuit, such as an SRAM or DRAM. The system uses a logic circuit to generate a non-interruptible burst of a predetermined number of internal address signals in response to a single external address, enabling high-speed data transfers.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-3, 8, 12-13, 16, and 17 by Wada

  • Prior Art Relied Upon: Wada (Patent 6,115,280).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Wada, which was not considered during the original prosecution, discloses every limitation of the independent claims. Wada teaches a semiconductor memory (SRAM) capable of burst operation using a "burst counter unit" that functions as the claimed logic circuit. This unit receives an external address, clock signal, and control signals to generate a predetermined number of internal address signals. Critically, Petitioner asserted that Wada's burst operation is non-interruptible, describing data output "without interruption therebetween" and noting an object of the invention is to provide high-speed read operations "without causing data output interruptions." Wada’s embodiments show a continuous generation of internal address values for the duration of the burst, with no disclosed mechanism for termination once initiated. This directly anticipates the core "non-interruptible" limitation that was key to the patent's allowance.

Ground 2: Obviousness of Claims 1-4, 8, 12-14, 16, and 17 over Wada and Barrett

  • Prior Art Relied Upon: Wada (Patent 6,115,280), Barrett (Patent 5,584,033).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground was presented as an alternative to the anticipation argument. Wada disclosed the foundational memory architecture with a burst counter. Barrett explicitly taught that the "essential feature of burst communication is that the data transfer takes place at high speed and without interruption." Barrett described systems that transmit an "uninterrupted stream" of data words and claimed a burst data transmission comprised of a plurality of "uninterruptible streams." Petitioner argued that combining Barrett's explicit teachings on uninterruptible data streams with Wada's memory architecture rendered the challenged claims obvious.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Wada and Barrett because they share the common goal of achieving high-speed data transfers. To the extent any ambiguity existed in Wada regarding the possibility of interrupting a burst, a POSITA would look to art like Barrett, which teaches that preventing interruptions is the very purpose of burst transmission. Applying Barrett's teachings to Wada would improve transmission efficiency by minimizing overhead, providing a clear motivation for the combination.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in making Wada's burst non-interruptible, as it involved implementing a well-understood control scheme to achieve a known benefit in the art.

Ground 3: Obviousness of Claims 4-7 and 18-20 over Wada and Fujioka

  • Prior Art Relied Upon: Wada (Patent 6,115,280), Fujioka (Patent 6,185,149).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addressed dependent claims related to specific and programmable burst lengths. Wada taught a fixed burst length of four by dividing memory into four blocks. Fujioka taught increasing data throughput by increasing the burst length (e.g., to eight) and, importantly, making the burst length programmable late in the manufacturing process using techniques like laser-cut fuses or bond options to tie circuits to specific voltage levels.
    • Motivation to Combine: A POSITA would be motivated to modify Wada’s memory system with Fujioka’s teachings to achieve higher throughput, a primary goal of Wada. Fujioka demonstrated how to increase burst length from four to eight by increasing the number of memory banks activated, a direct and analogous modification to Wada's architecture. Furthermore, implementing Fujioka's method for programming the burst length at manufacturing would offer enhanced design flexibility, a well-known engineering benefit.
    • Expectation of Success: The combination involved applying known techniques (bond options, fuses) for programmability to a standard memory architecture to achieve a predictable increase in throughput and flexibility.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including combinations of Wada with Reeves (Patent 6,226,755) to address DRAM-specific limitations (claims 9-10, 21) and with Lysinger (Patent 5,784,331) to address the sharing of address busses (claims 11, 15). Tertiary combinations adding Barrett to these grounds were also presented.

4. Key Claim Construction Positions

  • "non-interruptible" (claims 1, 16, 17): This term was central to the patent's allowance over prior art during prosecution. Petitioner noted that in a prior litigation, the parties agreed this term means "cannot be stopped or terminated once initiated until the fixed number of internal addresses has been generated." Petitioner argued that its invalidity contentions succeed even under this narrower construction, as the primary reference (Wada) discloses bursts that are not stopped or terminated before completion.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-21 of the ’134 patent as unpatentable.