PTAB

IPR2020-00990

Advanced Micro Devices Inc v. Monterey Research LLC

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Petition
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1. Case Identification

2. Patent Overview

  • Title: Memory Cell Design and Method
  • Brief Description: The ’805 patent relates to the design and layout of a six-transistor Static Random Access Memory (SRAM) cell. The patent describes a specific arrangement of substantially oblong active regions, polysilicon structures, contacts, and interconnect layers intended to create a compact and efficient memory cell.

3. Grounds for Unpatentability

Ground 1: Obviousness over Oh - Claims 8, 10, 12, 16, 18, and 22-23 are obvious over Oh.

  • Prior Art Relied Upon: Oh (Patent 6,417,549).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Oh, which was not considered during prosecution or reexamination, discloses every limitation of the challenged claims. Oh teaches a six-transistor SRAM cell layout with four substantially oblong active regions arranged in parallel, nearly identical to the layout in the ’805 patent. Petitioner contended that Oh’s polysilicon gate structures (e.g., P20, P22) function as the claimed “substantially oblong local interconnects” because they connect multiple transistor gates, are arranged perpendicular to the active regions, and extend only partially across the memory cell. Furthermore, Oh’s “first metal layer” was asserted to be the claimed “single local interconnect layer,” as it contains conductive structures (e.g., P50, P60) corresponding to bitlines and other structures (e.g., P52, P62) corresponding to a global wordline, all within the same layer. The argument for dependent claims followed, asserting Oh discloses shared contacts (claim 10), common power/ground interconnects (claims 12 and 18), and specific transistor region arrangements (claims 16, 22, and 23).

Ground 2: Obviousness over Oh in view of CMOS Circuit Design - Claims 8, 10, 12, 16, 18, and 22-23 are obvious over Oh in combination with CMOS Circuit Design.

  • Prior Art Relied Upon: Oh (Patent 6,417,549) and CMOS Circuit Design (R. Jacob Baker et al., a 1998 textbook).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground reinforced the arguments from Ground 1, leveraging the CMOS Circuit Design textbook as evidence of the knowledge of a person of ordinary skill in the art (POSITA). Petitioner argued that while Oh inherently discloses the claimed features, a POSITA would also have found it obvious to apply the well-known, standard MOSIS scalable design rules detailed in CMOS Circuit Design to Oh’s SRAM layout. Applying these standard rules, which govern minimum feature sizes and spacing, would confirm that Oh’s structures (e.g., its polysilicon gates and metal interconnects) are “substantially oblong” as defined in the ’805 patent specification (e.g., having a length greater than three times the width). The textbook provides the explicit, routine design principles that a POSITA would use to implement and optimize a layout like the one disclosed in Oh, leading directly to the claimed invention.
    • Motivation to Combine: A POSITA would combine Oh and CMOS Circuit Design because both are directed to designing and fabricating CMOS SRAM cells. Oh’s stated goal was to create a design that can be manufactured by standard CMOS processes. CMOS Circuit Design is a foundational textbook that explicitly teaches these standard processes and scalable design rules (MOSIS) to achieve key industry goals: increased integration density, reduced chip area, improved manufacturing yield, and lower cost. A POSITA seeking to implement or improve upon Oh’s layout would have naturally consulted a standard reference like CMOS Circuit Design to ensure the design was optimized and compatible with common manufacturing techniques.
    • Expectation of Success: A POSITA would have had a high expectation of success. The combination involved applying known, predictable design rules from a standard textbook to a known type of circuit (SRAM) disclosed in Oh. Both references teach the use of standard materials and fabrication processes, such as photolithography. The result of applying these rules was merely the optimization of a known circuit architecture, which would yield predictable improvements in density and manufacturability without any technical uncertainty.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 8, 10, 12, 16, 18, and 22-23 of the ’805 patent as unpatentable under 35 U.S.C. §103.