PTAB

IPR2020-01003

SMIC Americas v. Innovative Foundry Technologies LLC

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1. Case Identification

2. Patent Overview

  • Title: Transistor Device Having an Enhanced Width Dimension and a Method of Making Same
  • Brief Description: The ’122 patent describes a semiconductor transistor designed to maximize drive current by increasing the effective channel width without increasing the device's footprint. This is achieved by forming a gate electrode that extends over and into a recess defined by a recessed isolation structure, such as a shallow trench isolation (STI) structure.

3. Grounds for Unpatentability

Ground 1: Anticipation - Claims 1-2 and 11-12 are anticipated by Yun.

  • Prior Art Relied Upon: Yun (Korean Laid-Open Patent Application No. KR1998-074469).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yun discloses every limitation of the challenged claims. Yun teaches increasing a transistor's current driving capability by increasing the channel width without increasing chip area. It explicitly discloses a transistor with recessed isolation regions (21a) that define a recess above them, and a gate electrode (61) and gate insulation layer (41) that extend into this recess to increase the effective channel width. Yun also discloses forming the transistor on a silicon substrate and includes source and drain regions, thereby meeting all limitations of independent claim 1 and its challenged dependents.

Ground 2: Obviousness over Yun and Wada - Claims 5 and 27 are obvious over Yun in view of Wada.

  • Prior Art Relied Upon: Yun (Korean Laid-Open Patent Application No. KR1998-074469) and Wada (Patent 5,859,466).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Yun teaches the core transistor structure of claims 1 and 23, including the recessed isolation structure. Wada, which is directed to techniques for isolating transistors, was argued to supply the specific trench dimensions recited in dependent claims 5 and 27. Specifically, Wada discloses forming isolation trenches with a width of 2000-5000 Å and a depth of 5000-15000 Å, which overlaps with or renders obvious the claimed ranges.
    • Motivation to Combine: A POSITA would combine these references to improve transistor isolation and performance. Yun provides a method to increase drive current, and Wada provides well-understood, specific trench dimensions for forming effective isolation structures needed for densely integrated circuits. A POSITA would have been motivated to apply Wada’s established trench dimensions to Yun’s structure to ensure robust device isolation, a critical factor for transistor performance.
    • Expectation of Success: A POSITA would have a high expectation of success because both references are in the same field of semiconductor fabrication and address complementary problems. Applying known trench dimensions from Wada to the isolation structure in Yun was presented as a predictable and routine design choice.

Ground 3: Obviousness over Yun and Lu - Claims 6-10, 13-14, 17-22, and 28-32 are obvious over Yun in view of Lu.

  • Prior Art Relied Upon: Yun (Korean Laid-Open Patent Application No. KR1998-074469) and Lu (Patent 6,009,023).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that this combination renders obvious claims requiring specific materials, thicknesses, and source/drain structures. While Yun provides the foundational transistor design, Lu teaches using polysilicon for the gate electrode (claims 6, 13, 28), specific thickness ranges for the gate electrode and gate insulation layer (claims 8, 9, 18, 19, 30, 31), and the use of source/drain extension implant regions (claims 10, 20, 32). Lu explicitly discloses these features to enhance transistor performance and reliability in modern semiconductor devices.
    • Motivation to Combine: A POSITA would combine Yun and Lu to improve upon Yun's "conventional" fabrication process and enhance overall transistor performance and reliability. As transistor dimensions shrank, it was well known to use specific materials like polysilicon and structures like lightly-doped drain (LDD) extensions to manage short-channel effects and improve reliability. Lu provides an explicit roadmap for these improvements, which a POSITA would have been motivated to apply to Yun's transistor design to create a more robust and higher-performing device.
    • Expectation of Success: Success would be expected as the proposed modifications involved implementing well-known, state-of-the-art fabrication techniques (taught by Lu) into a transistor architecture (taught by Yun). Both references operate in the same technical field, and the integration of these features was a predictable path toward improving device performance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on Saki (Patent 5,960,297) as the primary reference, both alone and in combination with Wada and Lu, relying on similar technology and combination rationales as those presented for Yun.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, asserting that the parallel district court proceedings were in their early stages, with a trial date not yet set. Petitioner also contended that the prior art presented in the IPR petition did not completely overlap with the invalidity contentions in the district court case. Finally, Petitioner emphasized the strength of the petition's grounds, arguing that they demonstrated a high likelihood of prevailing on the merits, which weighs in favor of institution.

5. Relief Requested

  • Petitioner requests institution of inter partes review and cancellation of claims 1-3, 5-14, 16-25, and 27-34 of the ’122 patent as unpatentable.